Simulation Results: rom_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.34 %
  • code
  • 98.54 %
  • assert
  • 95.49 %
  • func
  • 94.99 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 94.80 %
  • toggle
  • 99.54 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.270s 743.791us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 13.690s 320.838us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 10.030s 1064.102us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.090s 534.201us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.019us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.270s 766.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 10.030s 1064.102us 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.019us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.500s 1025.472us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.980s 536.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.020s 396.680us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 25.660s 818.827us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.340s 4163.688us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.380s 205.661us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.700s 790.158us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.700s 790.158us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 13.690s 320.838us 1 1 100.00
rom_ctrl_csr_rw 10.030s 1064.102us 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.019us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.050s 1072.880us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 13.690s 320.838us 1 1 100.00
rom_ctrl_csr_rw 10.030s 1064.102us 1 1 100.00
rom_ctrl_csr_aliasing 6.960s 546.019us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.050s 1072.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.400s 1105.135us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 457.840s 2982.807us 0 1 0.00
rom_ctrl_tl_intg_err 51.680s 1121.534us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 457.840s 2982.807us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 457.840s 2982.807us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 457.840s 2982.807us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 457.840s 2982.807us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.270s 743.791us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.270s 743.791us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.270s 743.791us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.680s 1121.534us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
rom_ctrl_kmac_err_chk 14.340s 4163.688us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 149.350s 3055.542us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.400s 1105.135us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 457.840s 2982.807us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 172.720s 15274.310us 1 1 100.00