Simulation Results: rstmgr

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.27 %
  • code
  • 99.33 %
  • assert
  • 97.72 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.120s 114.606us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.030s 84.993us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.960s 64.359us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.610s 272.281us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.190s 466.833us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.220s 194.416us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.960s 64.359us 1 1 100.00
rstmgr_csr_aliasing 2.190s 466.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.930s 189.195us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.920s 157.455us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.250s 210.617us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.310s 1786.788us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.310s 1786.788us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.310s 1786.788us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.310s 1786.788us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 24.210s 6708.378us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.210s 93.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.700s 477.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.700s 477.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.030s 84.993us 1 1 100.00
rstmgr_csr_rw 0.960s 64.359us 1 1 100.00
rstmgr_csr_aliasing 2.190s 466.833us 1 1 100.00
rstmgr_same_csr_outstanding 1.700s 220.989us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.030s 84.993us 1 1 100.00
rstmgr_csr_rw 0.960s 64.359us 1 1 100.00
rstmgr_csr_aliasing 2.190s 466.833us 1 1 100.00
rstmgr_same_csr_outstanding 1.700s 220.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_tl_intg_err 2.630s 915.957us 1 1 100.00
rstmgr_sec_cm 10.530s 8814.484us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.530s 8814.484us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.530s 8814.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.630s 915.957us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.250s 146.492us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.800s 1947.629us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.050s 302.404us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.530s 8814.484us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.960s 64.359us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.960s 64.359us 1 1 100.00