Simulation Results: spi_device

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.48 %
  • code
  • 93.31 %
  • assert
  • 88.59 %
  • func
  • 74.55 %
  • line
  • 99.08 %
  • branch
  • 98.33 %
  • cond
  • 96.26 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 5.070s 1701.020us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.150s 22.182us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.120s 91.683us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.130s 1814.443us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.590s 222.517us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.590s 93.196us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.120s 91.683us 1 1 100.00
spi_device_csr_aliasing 10.590s 222.517us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.770s 17.924us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.970s 210.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.920s 19.631us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.960s 7.014us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.860s 12.458us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.910s 79.496us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.910s 79.496us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.110s 11898.287us 1 1 100.00
spi_device_tpm_sts_read 0.730s 227.826us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 13.960s 1270.739us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.700s 1747.547us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.920s 1836.302us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.920s 1836.302us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.920s 554.541us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.920s 554.541us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.920s 554.541us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.920s 554.541us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.920s 554.541us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.640s 187.693us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 16.720s 3284.347us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 16.720s 3284.347us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 16.720s 3284.347us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 12.390s 3147.882us 1 1 100.00
spi_device_read_buffer_direct 3.230s 531.450us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 16.720s 3284.347us 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 36.450s 29420.562us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 11.110s 2552.350us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 11.110s 2552.350us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 5.070s 1701.020us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 58.030s 3552.095us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 282.650s 106851.092us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.840s 54.447us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.850s 12.628us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.170s 567.976us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.170s 567.976us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 22.182us 1 1 100.00
spi_device_csr_rw 2.120s 91.683us 1 1 100.00
spi_device_csr_aliasing 10.590s 222.517us 1 1 100.00
spi_device_same_csr_outstanding 2.340s 669.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 22.182us 1 1 100.00
spi_device_csr_rw 2.120s 91.683us 1 1 100.00
spi_device_csr_aliasing 10.590s 222.517us 1 1 100.00
spi_device_same_csr_outstanding 2.340s 669.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 14.140s 1561.350us 1 1 100.00
spi_device_sec_cm 1.020s 155.013us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.140s 1561.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 39.120s 17147.800us 1 1 100.00