Simulation Results: spi_host

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 94.69 %
  • assert
  • 93.54 %
  • func
  • 88.75 %
  • block
  • 96.50 %
  • line
  • 98.30 %
  • branch
  • 92.65 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 21.000s 3257.156us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 20.587us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 21.292us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 90.618us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 27.982us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 41.533us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 21.292us 1 1 100.00
spi_host_csr_aliasing 1.000s 27.982us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 16.439us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 63.411us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 60.947us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 5.000s 207.677us 1 1 100.00
spi_host_error_cmd 1.000s 19.440us 1 1 100.00
spi_host_event 6.000s 1122.827us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 145.371us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 145.371us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 145.371us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 10.000s 551.033us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 54.018us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 145.371us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 145.371us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 21.000s 3257.156us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 21.000s 3257.156us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 7.000s 850.164us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 1639.355us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 35.000s 2970.505us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 4.000s 121.460us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 5.000s 207.677us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 20.410us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 19.542us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 80.133us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 80.133us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 20.587us 1 1 100.00
spi_host_csr_rw 2.000s 21.292us 1 1 100.00
spi_host_csr_aliasing 1.000s 27.982us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 28.400us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 20.587us 1 1 100.00
spi_host_csr_rw 2.000s 21.292us 1 1 100.00
spi_host_csr_aliasing 1.000s 27.982us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 28.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 508.448us 1 1 100.00
spi_host_tl_intg_err 2.000s 353.885us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 353.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 14.000s 1234.858us 1 1 100.00