Simulation Results: sram_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.15 %
  • code
  • 90.40 %
  • assert
  • 95.55 %
  • func
  • 93.51 %
  • line
  • 97.77 %
  • branch
  • 95.79 %
  • cond
  • 91.55 %
  • toggle
  • 90.71 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 33.850s 3583.151us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.670s 42.283us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.670s 16.638us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.360s 82.734us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 33.559us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.710s 1378.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.670s 16.638us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 33.559us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 124.050s 46985.194us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 46.120s 991.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 421.890s 16080.977us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 161.690s 3527.771us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1297.140s 153728.609us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 354.400s 14913.637us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 18.290s 18424.661us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 80.570s 4175.473us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.600s 526.291us 1 1 100.00
sram_ctrl_partial_access_b2b 160.130s 19044.258us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.400s 680.961us 1 1 100.00
sram_ctrl_throughput_w_partial_write 33.430s 783.297us 1 1 100.00
sram_ctrl_throughput_w_readback 50.420s 5080.009us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 635.750s 64041.326us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.120s 1296.177us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1834.440s 190717.881us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.630s 36.732us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.950s 321.740us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.950s 321.740us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.670s 42.283us 1 1 100.00
sram_ctrl_csr_rw 0.670s 16.638us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 33.559us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 25.926us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.670s 42.283us 1 1 100.00
sram_ctrl_csr_rw 0.670s 16.638us 1 1 100.00
sram_ctrl_csr_aliasing 0.640s 33.559us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 25.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.860s 15449.695us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.630s 9.941us 0 1 0.00
sram_ctrl_tl_intg_err 1.910s 206.614us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.630s 9.941us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.910s 206.614us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 635.750s 64041.326us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 635.750s 64041.326us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.670s 16.638us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 80.570s 4175.473us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 80.570s 4175.473us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 80.570s 4175.473us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 18.290s 18424.661us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.610s 667.392us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.860s 15449.695us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.740s 794.965us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 33.850s 3583.151us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 33.850s 3583.151us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 80.570s 4175.473us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.630s 9.941us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 18.290s 18424.661us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.630s 9.941us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.630s 9.941us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 33.850s 3583.151us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.630s 9.941us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.720s 650.270us 1 1 100.00