Simulation Results: sram_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.98 %
  • code
  • 89.36 %
  • assert
  • 95.51 %
  • func
  • 94.06 %
  • line
  • 97.40 %
  • branch
  • 94.95 %
  • cond
  • 92.53 %
  • toggle
  • 90.47 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.430s 270.699us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.740s 33.092us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.670s 12.019us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.660s 486.535us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 17.950us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.920s 25.840us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.670s 12.019us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 17.950us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.190s 543.533us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.310s 747.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 499.530s 6943.107us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 189.560s 33062.467us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 17.880s 9509.886us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 589.840s 29839.034us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.790s 1497.429us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 474.960s 52006.061us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 25.220s 160.203us 1 1 100.00
sram_ctrl_partial_access_b2b 167.680s 12706.110us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 44.470s 124.301us 1 1 100.00
sram_ctrl_throughput_w_partial_write 22.670s 411.986us 1 1 100.00
sram_ctrl_throughput_w_readback 49.110s 2133.362us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 59.670s 2017.680us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.740s 89.330us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1596.300s 12474.042us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.680s 13.383us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.760s 206.859us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.760s 206.859us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 33.092us 1 1 100.00
sram_ctrl_csr_rw 0.670s 12.019us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 17.950us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 71.317us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 33.092us 1 1 100.00
sram_ctrl_csr_rw 0.670s 12.019us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 17.950us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.720s 71.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.620s 813.367us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.580s 3.418us 0 1 0.00
sram_ctrl_tl_intg_err 1.210s 322.470us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.580s 3.418us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.210s 322.470us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 59.670s 2017.680us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 59.670s 2017.680us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.670s 12.019us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 474.960s 52006.061us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 474.960s 52006.061us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 474.960s 52006.061us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.790s 1497.429us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.070s 176.501us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.620s 813.367us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.050s 171.768us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.430s 270.699us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.430s 270.699us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 474.960s 52006.061us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.580s 3.418us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.790s 1497.429us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.580s 3.418us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.580s 3.418us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.430s 270.699us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.580s 3.418us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 62.830s 498.559us 1 1 100.00