Simulation Results: sysrst_ctrl

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.09 %
  • assert
  • 94.92 %
  • func
  • 61.94 %
  • line
  • 97.60 %
  • branch
  • 97.63 %
  • cond
  • 95.20 %
  • toggle
  • 100.00 %
  • FSM
  • 75.00 %
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.010s 2170.513us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.330s 2442.649us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.330s 2206.823us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.320s 2541.672us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.920s 6090.982us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.780s 2038.538us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 33.670s 32676.940us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2728.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.960s 2083.922us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.780s 2038.538us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2728.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 198.010s 104516.758us 1 1 100.00
combo_detect_with_pre_cond 0 1 0.00
sysrst_ctrl_combo_detect_with_pre_cond 105.470s 212712.962us 0 1 0.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.230s 3771.967us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 0.860s 3872.899us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.930s 2507.984us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.790s 2092.155us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.080s 4762.462us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.630s 2611.486us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.720s 7314.989us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 26.710s 35680.924us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 6.280s 6746.145us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.400s 2038.213us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 5.330s 2011.182us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.070s 2068.606us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.070s 2068.606us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.920s 6090.982us 1 1 100.00
sysrst_ctrl_csr_rw 4.780s 2038.538us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2728.123us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.000s 5302.527us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.920s 6090.982us 1 1 100.00
sysrst_ctrl_csr_rw 4.780s 2038.538us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.920s 2728.123us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.000s 5302.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 87.080s 42011.468us 1 1 100.00
sysrst_ctrl_tl_intg_err 17.190s 42588.622us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 17.190s 42588.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.830s 4664.155us 1 1 100.00