Simulation Results: uart

 
26/11/2025 18:41:30 sha: b4301fc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.56 %
  • code
  • 94.89 %
  • assert
  • 96.83 %
  • func
  • 49.97 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 93.12 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.630s 266.691us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.740s 53.753us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.730s 73.430us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.930s 59.041us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.850s 53.810us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.050s 66.309us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.730s 73.430us 1 1 100.00
uart_csr_aliasing 0.850s 53.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 30.330s 92571.136us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.630s 266.691us 1 1 100.00
uart_tx_rx 30.330s 92571.136us 1 1 100.00
parity_error 2 2 100.00
uart_intr 3.310s 6402.640us 1 1 100.00
uart_rx_parity_err 77.280s 144565.589us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 30.330s 92571.136us 1 1 100.00
uart_intr 3.310s 6402.640us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 27.250s 21981.068us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 42.350s 100119.430us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 29.440s 156505.971us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 3.310s 6402.640us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 3.310s 6402.640us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 3.310s 6402.640us 1 1 100.00
perf 1 1 100.00
uart_perf 868.100s 33688.854us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 14.640s 10088.120us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 14.640s 10088.120us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.170s 2802.452us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 1835.398us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 12.610s 8033.489us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 15.140s 4318.422us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 192.040s 73298.688us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 121.290s 96366.568us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.740s 41.228us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.810s 14.764us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.470s 44.004us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.470s 44.004us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.740s 53.753us 1 1 100.00
uart_csr_rw 0.730s 73.430us 1 1 100.00
uart_csr_aliasing 0.850s 53.810us 1 1 100.00
uart_same_csr_outstanding 0.760s 35.790us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.740s 53.753us 1 1 100.00
uart_csr_rw 0.730s 73.430us 1 1 100.00
uart_csr_aliasing 0.850s 53.810us 1 1 100.00
uart_same_csr_outstanding 0.760s 35.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_tl_intg_err 1.380s 117.108us 1 1 100.00
uart_sec_cm 1.200s 439.511us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.380s 117.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 9.750s 666.087us 1 1 100.00