Simulation Results: adc_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.74 %
  • code
  • 97.50 %
  • assert
  • 95.79 %
  • func
  • 33.92 %
  • line
  • 99.02 %
  • branch
  • 98.58 %
  • cond
  • 95.29 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.020s 5841.494us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.020s 915.770us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.390s 470.705us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 72.690s 43886.533us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 465.452us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.980s 726.425us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.390s 470.705us 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 465.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 85.130s 160937.276us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 276.520s 169370.149us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 557.680s 509143.087us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 271.500s 167382.287us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 152.350s 363882.182us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 160.110s 401168.148us 1 1 100.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1050.540s 600000.000us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 144.490s 2000000.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.690s 4671.022us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 33.080s 41135.862us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 108.430s 129104.936us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 6.750s 13222.757us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.010s 494.814us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.780s 385.222us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.930s 386.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.930s 386.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.020s 915.770us 1 1 100.00
adc_ctrl_csr_rw 1.390s 470.705us 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 465.452us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.190s 2716.310us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.020s 915.770us 1 1 100.00
adc_ctrl_csr_rw 1.390s 470.705us 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 465.452us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.190s 2716.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 9.130s 8451.066us 1 1 100.00
adc_ctrl_sec_cm 4.830s 3834.092us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.130s 8451.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.710s 4271.777us 1 1 100.00