Simulation Results: csrng

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.16 %
  • code
  • 86.28 %
  • assert
  • 91.95 %
  • func
  • 77.25 %
  • block
  • 96.63 %
  • line
  • 97.37 %
  • branch
  • 91.83 %
  • toggle
  • 91.65 %
  • FSM
  • 64.29 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 41.001us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 16.859us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 63.109us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 130.021us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 47.209us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 28.453us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 63.109us 1 1 100.00
csrng_csr_aliasing 3.000s 47.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 633.648us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 24.000s 1502.837us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 24.000s 1502.837us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 76.000s 3556.829us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 55.854us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 23.016us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 97.646us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 97.646us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.859us 1 1 100.00
csrng_csr_rw 3.000s 63.109us 1 1 100.00
csrng_csr_aliasing 3.000s 47.209us 1 1 100.00
csrng_same_csr_outstanding 3.000s 42.731us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.859us 1 1 100.00
csrng_csr_rw 3.000s 63.109us 1 1 100.00
csrng_csr_aliasing 3.000s 47.209us 1 1 100.00
csrng_same_csr_outstanding 3.000s 42.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 23.000s 749.420us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 3.000s 63.109us 1 1 100.00
csrng_regwen 3.000s 23.757us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 633.648us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 76.000s 3556.829us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 633.648us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 76.000s 3556.829us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 633.648us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 23.000s 749.420us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
csrng_sec_cm 2.000s 71.174us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 279.009us 1 1 100.00
csrng_err 2.000s 29.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 220.000s 11622.778us 1 1 100.00