Simulation Results: edn

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 86.76 %
  • assert
  • 97.56 %
  • func
  • 79.01 %
  • line
  • 98.30 %
  • branch
  • 94.72 %
  • cond
  • 90.26 %
  • toggle
  • 96.46 %
  • FSM
  • 54.07 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.050s 19.296us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.150s 130.664us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 14.617us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.760s 506.097us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 77.238us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.100s 18.136us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 14.617us 1 1 100.00
edn_csr_aliasing 1.200s 77.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.440s 72.472us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.440s 72.472us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.440s 72.472us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.930s 69.550us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 35.038us 1 1 100.00
errs 1 1 100.00
edn_err 1.160s 20.245us 1 1 100.00
disable 2 2 100.00
edn_disable 0.920s 164.080us 1 1 100.00
edn_disable_auto_req_mode 1.190s 36.697us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.150s 734.767us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 13.589us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 23.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.890s 52.267us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.890s 52.267us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.150s 130.664us 1 1 100.00
edn_csr_rw 0.890s 14.617us 1 1 100.00
edn_csr_aliasing 1.200s 77.238us 1 1 100.00
edn_same_csr_outstanding 0.930s 16.783us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.150s 130.664us 1 1 100.00
edn_csr_rw 0.890s 14.617us 1 1 100.00
edn_csr_aliasing 1.200s 77.238us 1 1 100.00
edn_same_csr_outstanding 0.930s 16.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.440s 54.735us 1 1 100.00
edn_sec_cm 3.850s 305.543us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 39.351us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 35.038us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.850s 305.543us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.850s 305.543us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.850s 305.543us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.850s 305.543us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 35.038us 1 1 100.00
edn_sec_cm 3.850s 305.543us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 35.038us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.440s 54.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 64.920s 4055.521us 1 1 100.00