| V1 |
|
100.00% |
| V2 |
|
96.92% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 63.380s | 126.038us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 8.290s | 91.284us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 14.060s | 186.436us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 37.950s | 2538.739us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 22.530s | 2655.840us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 8.940s | 162.763us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 22.530s | 2655.840us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 5.320s | 54.871us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 5.180s | 18.605us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 8.460s | 187.837us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 21.120s | 122.398us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1191.910s | 571355.700us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 571.660s | 50136.419us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 5.250s | 76.370us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 1153.100s | 420702.860us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 228.970s | 2814.333us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 114.000s | 2628.137us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 1845.010s | 153378.151us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 36.220s | 648.305us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 2 | 3 | 66.67 | |||
| flash_ctrl_rw_evict | 12.760s | 14.391us | 0 | 1 | 0.00 | |
| flash_ctrl_rw_evict_all_en | 11.470s | 43.408us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 14.170s | 60.190us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 88.240s | 605.588us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 88.240s | 605.588us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 230.290s | 5784.851us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 12.740s | 547.116us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 337.890s | 303.957us | 1 | 1 | 100.00 | |
| error_mp | 0 | 1 | 0.00 | |||
| flash_ctrl_error_mp | 71.080s | 1889.883us | 0 | 1 | 0.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 288.010s | 1393.373us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 1080.130s | 6296.927us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 6.000s | 42.384us | 1 | 1 | 100.00 | |
| read_write_overflow | 1 | 1 | 100.00 | |||
| flash_ctrl_oversize_error | 118.230s | 6752.936us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 9.220s | 35.336us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 6.730s | 27.573us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 601.090s | 284.471us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 57.060s | 2700.797us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 37.860s | 75.812us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1191.910s | 571355.700us | 1 | 1 | 100.00 | |
| interrupts | 4 | 4 | 100.00 | |||
| flash_ctrl_intr_rd | 70.540s | 688.782us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 54.240s | 3235.506us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 76.210s | 10692.912us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 120.020s | 46548.751us | 1 | 1 | 100.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 42.870s | 920.484us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 43.650s | 18967.694us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 9.540s | 27.147us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 80.310s | 760.091us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 154.270s | 4273.680us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 103.550s | 798.832us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 348.600s | 19696.053us | 1 | 1 | 100.00 | |
| single_bit_err | 3 | 3 | 100.00 | |||
| flash_ctrl_read_word_sweep_serr | 9.270s | 27.177us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 80.040s | 4502.446us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 115.330s | 4054.300us | 1 | 1 | 100.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 40.730s | 630.786us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 45.930s | 2424.182us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 99.770s | 2311.822us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 6.390s | 306.982us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 5.850s | 63.206us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 67.580s | 1147.792us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 386.680s | 5136.184us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 21.950s | 1194.752us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 608.520s | 124413.261us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 94.840s | 10019.431us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 5.490s | 501.161us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 5.090s | 17.209us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 8.930s | 244.348us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 8.930s | 244.348us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 14.060s | 186.436us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 22.530s | 2655.840us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 15.880s | 250.400us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 14.060s | 186.436us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 22.530s | 2655.840us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 15.880s | 250.400us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 16.100s | 340.358us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_tl_intg_err | 347.610s | 696.577us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 347.610s | 696.577us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 347.610s | 696.577us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.770s | 241.226us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 6.780s | 178.610us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 63.380s | 126.038us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 37.860s | 75.812us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 9.220s | 35.336us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 36.920s | 2651.167us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 6.730s | 27.573us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 5.600s | 47.176us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 6.060s | 83.624us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 28.940s | 97.928us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 9.220s | 35.336us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.770s | 241.226us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 5.390s | 98.027us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 12.970s | 48.106us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 9.220s | 35.336us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 12.740s | 547.116us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 386.680s | 5136.184us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_serr | 115.330s | 4054.300us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 154.270s | 4273.680us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 348.600s | 19696.053us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1191.910s | 571355.700us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 11.570s | 721.841us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_host_grant_err | 5.570s | 39.548us | 1 | 1 | 100.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 5.660s | 43.114us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1514.700s | 2040.959us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 17.460s | 150.919us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 286.380s | 863.073us | 1 | 1 | 100.00 | |