Simulation Results: hmac

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.32 %
  • code
  • 97.76 %
  • assert
  • 96.18 %
  • func
  • 44.02 %
  • line
  • 99.74 %
  • branch
  • 99.01 %
  • cond
  • 95.95 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.220s 468.416us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.750s 46.891us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.700s 50.385us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.900s 816.052us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.620s 617.268us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.900s 44.047us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.700s 50.385us 1 1 100.00
hmac_csr_aliasing 5.620s 617.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 59.270s 19872.611us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 8.810s 871.999us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 192.210s 27478.044us 1 1 100.00
hmac_test_sha384_vectors 18.940s 1264.225us 1 1 100.00
hmac_test_sha512_vectors 18.360s 817.429us 1 1 100.00
hmac_test_hmac256_vectors 6.150s 221.944us 1 1 100.00
hmac_test_hmac384_vectors 7.840s 266.099us 1 1 100.00
hmac_test_hmac512_vectors 9.390s 1134.851us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 20.190s 8652.772us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 713.530s 95527.101us 1 1 100.00
error 1 1 100.00
hmac_error 25.690s 2656.207us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 78.230s 98297.883us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.220s 468.416us 1 1 100.00
hmac_long_msg 59.270s 19872.611us 1 1 100.00
hmac_back_pressure 8.810s 871.999us 1 1 100.00
hmac_datapath_stress 713.530s 95527.101us 1 1 100.00
hmac_burst_wr 20.190s 8652.772us 1 1 100.00
hmac_stress_all 224.690s 67627.563us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.220s 468.416us 1 1 100.00
hmac_long_msg 59.270s 19872.611us 1 1 100.00
hmac_back_pressure 8.810s 871.999us 1 1 100.00
hmac_datapath_stress 713.530s 95527.101us 1 1 100.00
hmac_wipe_secret 78.230s 98297.883us 1 1 100.00
hmac_test_sha256_vectors 192.210s 27478.044us 1 1 100.00
hmac_test_sha384_vectors 18.940s 1264.225us 1 1 100.00
hmac_test_sha512_vectors 18.360s 817.429us 1 1 100.00
hmac_test_hmac256_vectors 6.150s 221.944us 1 1 100.00
hmac_test_hmac384_vectors 7.840s 266.099us 1 1 100.00
hmac_test_hmac512_vectors 9.390s 1134.851us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.220s 468.416us 1 1 100.00
hmac_long_msg 59.270s 19872.611us 1 1 100.00
hmac_back_pressure 8.810s 871.999us 1 1 100.00
hmac_datapath_stress 713.530s 95527.101us 1 1 100.00
hmac_burst_wr 20.190s 8652.772us 1 1 100.00
hmac_error 25.690s 2656.207us 1 1 100.00
hmac_wipe_secret 78.230s 98297.883us 1 1 100.00
hmac_test_sha256_vectors 192.210s 27478.044us 1 1 100.00
hmac_test_sha384_vectors 18.940s 1264.225us 1 1 100.00
hmac_test_sha512_vectors 18.360s 817.429us 1 1 100.00
hmac_test_hmac256_vectors 6.150s 221.944us 1 1 100.00
hmac_test_hmac384_vectors 7.840s 266.099us 1 1 100.00
hmac_test_hmac512_vectors 9.390s 1134.851us 1 1 100.00
hmac_stress_all 224.690s 67627.563us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 224.690s 67627.563us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.720s 21.965us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.750s 79.455us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.760s 96.091us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.760s 96.091us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.750s 46.891us 1 1 100.00
hmac_csr_rw 0.700s 50.385us 1 1 100.00
hmac_csr_aliasing 5.620s 617.268us 1 1 100.00
hmac_same_csr_outstanding 1.670s 104.792us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.750s 46.891us 1 1 100.00
hmac_csr_rw 0.700s 50.385us 1 1 100.00
hmac_csr_aliasing 5.620s 617.268us 1 1 100.00
hmac_same_csr_outstanding 1.670s 104.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.830s 152.711us 1 1 100.00
hmac_tl_intg_err 2.200s 97.698us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.200s 97.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.220s 468.416us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.230s 432.742us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 162.340s 87221.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.740s 42.798us 1 1 100.00