Simulation Results: lc_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.42 %
  • code
  • 84.24 %
  • assert
  • 93.99 %
  • func
  • 90.04 %
  • line
  • 97.08 %
  • branch
  • 93.67 %
  • cond
  • 79.10 %
  • toggle
  • 81.13 %
  • FSM
  • 70.21 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.580s 53.052us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 51.321us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 16.338us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.390s 55.925us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.890s 65.231us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.110s 23.340us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 16.338us 1 1 100.00
lc_ctrl_csr_aliasing 0.890s 65.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.800s 1451.906us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.550s 3017.137us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.080s 23.226us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.880s 96.543us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.810s 382.374us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_prog_failure 1.880s 96.543us 1 1 100.00
lc_ctrl_errors 7.810s 382.374us 1 1 100.00
lc_ctrl_security_escalation 5.420s 3298.533us 1 1 100.00
lc_ctrl_jtag_state_failure 4.250s 159.278us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.460s 150.185us 1 1 100.00
lc_ctrl_jtag_errors 24.100s 1191.332us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.180s 915.733us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.150s 322.484us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.460s 150.185us 1 1 100.00
lc_ctrl_jtag_errors 24.100s 1191.332us 1 1 100.00
lc_ctrl_jtag_access 6.780s 325.492us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.940s 910.952us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.750s 491.866us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.760s 222.747us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.200s 6963.797us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.850s 644.191us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.880s 22.302us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.810s 119.810us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 26.193us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.600s 3614.556us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 45.226us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 271.960s 36210.907us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.970s 54.568us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.820s 105.611us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.820s 105.611us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 51.321us 1 1 100.00
lc_ctrl_csr_rw 0.760s 16.338us 1 1 100.00
lc_ctrl_csr_aliasing 0.890s 65.231us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 20.396us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 51.321us 1 1 100.00
lc_ctrl_csr_rw 0.760s 16.338us 1 1 100.00
lc_ctrl_csr_aliasing 0.890s 65.231us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 20.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
lc_ctrl_tl_intg_err 1.490s 173.512us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.490s 173.512us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.550s 3017.137us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.260s 127.892us 0 1 0.00
lc_ctrl_sec_cm 8.250s 1254.298us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.420s 3298.533us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.800s 1451.906us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.150s 322.484us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.330s 356.263us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.330s 356.263us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.120s 1356.428us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.300s 2188.729us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.300s 2188.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.400s 71.462us 0 1 0.00