Simulation Results: lc_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.60 %
  • code
  • 82.67 %
  • assert
  • 93.85 %
  • func
  • 83.27 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 79.28 %
  • toggle
  • 73.90 %
  • FSM
  • 69.47 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.610s 36.100us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.910s 26.311us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.735us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.380s 162.998us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 34.989us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.390s 26.542us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 15.735us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 34.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.350s 74.231us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.420s 392.484us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.750s 39.449us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.160s 132.079us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.490s 292.857us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_prog_failure 2.160s 132.079us 1 1 100.00
lc_ctrl_errors 4.490s 292.857us 1 1 100.00
lc_ctrl_security_escalation 6.870s 1503.323us 1 1 100.00
lc_ctrl_jtag_state_failure 4.380s 819.504us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.030s 1303.715us 1 1 100.00
lc_ctrl_jtag_errors 35.900s 17094.557us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.860s 1001.324us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.120s 340.982us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.030s 1303.715us 1 1 100.00
lc_ctrl_jtag_errors 35.900s 17094.557us 1 1 100.00
lc_ctrl_jtag_access 1.020s 203.365us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.680s 853.663us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.550s 94.131us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.570s 46.220us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 21.960s 2152.892us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 14.470s 987.568us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.940s 162.842us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.790s 65.877us 1 1 100.00
lc_ctrl_jtag_alert_test 1.060s 254.622us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.250s 2106.798us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.700s 40.823us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 3.140s 43.211us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.890s 20.441us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.050s 129.723us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.050s 129.723us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.910s 26.311us 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.735us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 34.989us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 22.921us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.910s 26.311us 1 1 100.00
lc_ctrl_csr_rw 0.810s 15.735us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 34.989us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 22.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
lc_ctrl_tl_intg_err 1.280s 349.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.280s 349.485us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.420s 392.484us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.290s 93.130us 0 1 0.00
lc_ctrl_sec_cm 7.250s 943.498us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.870s 1503.323us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.350s 74.231us 0 1 0.00
lc_ctrl_jtag_state_post_trans 4.120s 340.982us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.380s 745.313us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.380s 745.313us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.940s 219.643us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.720s 2312.461us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.720s 2312.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.010s 65.626us 0 1 0.00