Simulation Results: pattgen

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 19.000s 90.045us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 12.000s 33.075us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 17.000s 43.084us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 14.000s 775.379us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 8.000s 21.120us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 3.000s 77.742us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 17.000s 43.084us 1 1 100.00
pattgen_csr_aliasing 8.000s 21.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 45.000s 2755.029us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 27.000s 8041.475us 1 1 100.00
error 1 1 100.00
pattgen_error 15.000s 30.952us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 10.000s 77.670us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 14.000s 13.078us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 12.000s 22.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 14.000s 46.976us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 14.000s 46.976us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 12.000s 33.075us 1 1 100.00
pattgen_csr_rw 17.000s 43.084us 1 1 100.00
pattgen_csr_aliasing 8.000s 21.120us 1 1 100.00
pattgen_same_csr_outstanding 7.000s 69.036us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 12.000s 33.075us 1 1 100.00
pattgen_csr_rw 17.000s 43.084us 1 1 100.00
pattgen_csr_aliasing 8.000s 21.120us 1 1 100.00
pattgen_same_csr_outstanding 7.000s 69.036us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 12.000s 149.399us 1 1 100.00
pattgen_tl_intg_err 12.000s 47.947us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 12.000s 47.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 45.000s 11317.357us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 13.000s 714.469us 1 1 100.00