Simulation Results: pwrmgr

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.58 %
  • code
  • 94.46 %
  • assert
  • 96.08 %
  • func
  • 96.21 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 93.92 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.650s 38.036us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.620s 32.407us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.770s 20.979us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.560s 114.881us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.980s 42.338us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.780s 37.707us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.770s 20.979us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 42.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.720s 100.433us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.720s 100.433us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.960s 38.123us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 71.497us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.660s 25.939us 1 1 100.00
pwrmgr_reset_invalid 0.760s 100.171us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.660s 25.939us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.810s 204.284us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.890s 147.163us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.790s 80.125us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.560s 761.168us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.610s 33.067us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.420s 277.342us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.420s 277.342us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 32.407us 1 1 100.00
pwrmgr_csr_rw 0.770s 20.979us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 42.338us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 28.823us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 32.407us 1 1 100.00
pwrmgr_csr_rw 0.770s 20.979us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 42.338us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 28.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.620s 10.947us 0 1 0.00
pwrmgr_sec_cm 0.720s 14.996us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.720s 14.996us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.720s 14.996us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.620s 10.947us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.480s 2168.063us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.810s 204.284us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.740s 81.002us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 30.718us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.720s 14.996us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.720s 14.996us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.720s 14.996us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 70.472us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.580s 42.869us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.760s 124.716us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.770s 20.979us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.770s 20.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.700s 136.709us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.460s 3058.792us 1 1 100.00