Simulation Results: rom_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.44 %
  • code
  • 97.88 %
  • assert
  • 95.49 %
  • func
  • 95.94 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 93.16 %
  • toggle
  • 98.62 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.970s 181.170us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.580s 403.048us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.010s 169.874us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.570s 497.265us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.360s 130.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.440s 540.342us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.010s 169.874us 1 1 100.00
rom_ctrl_csr_aliasing 3.360s 130.772us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.840s 593.071us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.810s 438.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.690s 582.771us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.240s 581.595us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.240s 714.613us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.240s 385.359us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.450s 1701.237us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.450s 1701.237us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.580s 403.048us 1 1 100.00
rom_ctrl_csr_rw 4.010s 169.874us 1 1 100.00
rom_ctrl_csr_aliasing 3.360s 130.772us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.670s 1084.837us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.580s 403.048us 1 1 100.00
rom_ctrl_csr_rw 4.010s 169.874us 1 1 100.00
rom_ctrl_csr_aliasing 3.360s 130.772us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.670s 1084.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.770s 2995.424us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_tl_intg_err 21.530s 216.022us 1 1 100.00
rom_ctrl_sec_cm 196.350s 2070.864us 0 1 0.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 196.350s 2070.864us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 196.350s 2070.864us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 196.350s 2070.864us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 196.350s 2070.864us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.970s 181.170us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.970s 181.170us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.970s 181.170us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.530s 216.022us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
rom_ctrl_kmac_err_chk 8.240s 714.613us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 93.600s 6827.528us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.770s 2995.424us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 196.350s 2070.864us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 186.230s 4366.226us 1 1 100.00