Simulation Results: rom_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 98.55 %
  • assert
  • 95.49 %
  • func
  • 94.51 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 94.95 %
  • toggle
  • 99.06 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.070s 309.925us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.130s 738.830us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.800s 558.635us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.260s 294.182us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.540s 1138.389us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.410s 213.113us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.800s 558.635us 1 1 100.00
rom_ctrl_csr_aliasing 5.540s 1138.389us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.030s 727.373us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.570s 302.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.900s 571.966us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.730s 841.517us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.400s 1060.537us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.020s 210.740us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.750s 589.949us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.750s 589.949us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.130s 738.830us 1 1 100.00
rom_ctrl_csr_rw 6.800s 558.635us 1 1 100.00
rom_ctrl_csr_aliasing 5.540s 1138.389us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.760s 749.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.130s 738.830us 1 1 100.00
rom_ctrl_csr_rw 6.800s 558.635us 1 1 100.00
rom_ctrl_csr_aliasing 5.540s 1138.389us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.760s 749.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.850s 10151.942us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 240.570s 1630.575us 0 1 0.00
rom_ctrl_tl_intg_err 50.230s 409.952us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 240.570s 1630.575us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 240.570s 1630.575us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 240.570s 1630.575us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 240.570s 1630.575us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.070s 309.925us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.070s 309.925us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.070s 309.925us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.230s 409.952us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
rom_ctrl_kmac_err_chk 14.400s 1060.537us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 96.380s 2831.433us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.850s 10151.942us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 240.570s 1630.575us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 27.000s 949.591us 1 1 100.00