Simulation Results: rstmgr

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.58 %
  • code
  • 99.38 %
  • assert
  • 97.86 %
  • func
  • 98.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.110s 198.696us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.710s 109.821us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.750s 85.996us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.130s 797.707us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.450s 153.242us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.190s 167.413us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.750s 85.996us 1 1 100.00
rstmgr_csr_aliasing 1.450s 153.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.670s 114.372us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.520s 373.496us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.990s 145.775us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.450s 1792.210us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.450s 1792.210us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.450s 1792.210us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.450s 1792.210us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.610s 9228.236us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.740s 74.748us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.300s 128.939us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.300s 128.939us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.710s 109.821us 1 1 100.00
rstmgr_csr_rw 0.750s 85.996us 1 1 100.00
rstmgr_csr_aliasing 1.450s 153.242us 1 1 100.00
rstmgr_same_csr_outstanding 1.190s 207.750us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.710s 109.821us 1 1 100.00
rstmgr_csr_rw 0.750s 85.996us 1 1 100.00
rstmgr_csr_aliasing 1.450s 153.242us 1 1 100.00
rstmgr_same_csr_outstanding 1.190s 207.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.640s 16852.758us 1 1 100.00
rstmgr_tl_intg_err 2.450s 887.905us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.640s 16852.758us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.640s 16852.758us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.450s 887.905us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.950s 191.536us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.260s 1276.657us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.970s 301.870us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.640s 16852.758us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.750s 85.996us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.750s 85.996us 1 1 100.00