| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
66.67% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 1 | 1 | 100.00 | |||
| rv_timer_random | 0.830s | 311.460us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.530s | 33.895us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| rv_timer_csr_rw | 0.530s | 41.330us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.630s | 64.799us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.650s | 49.061us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.630s | 12.738us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| rv_timer_csr_rw | 0.530s | 41.330us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.650s | 49.061us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.800s | 1190.624us | 0 | 1 | 0.00 | |
| disabled | 1 | 1 | 100.00 | |||
| rv_timer_disabled | 1.560s | 1688.233us | 1 | 1 | 100.00 | |
| cfg_update_on_fly | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 278.060s | 441888.146us | 1 | 1 | 100.00 | |
| no_interrupt_test | 1 | 1 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 278.060s | 441888.146us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| rv_timer_stress_all | 1.090s | 3156.581us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| rv_timer_alert_test | 0.540s | 55.795us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| rv_timer_intr_test | 0.560s | 44.625us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.120s | 108.628us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| rv_timer_tl_errors | 1.120s | 108.628us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.530s | 33.895us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.530s | 41.330us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.650s | 49.061us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.570s | 59.536us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.530s | 33.895us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.530s | 41.330us | 1 | 1 | 100.00 | |
| rv_timer_csr_aliasing | 0.650s | 49.061us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.570s | 59.536us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| rv_timer_sec_cm | 0.680s | 247.068us | 1 | 1 | 100.00 | |
| rv_timer_tl_intg_err | 0.970s | 286.122us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| rv_timer_tl_intg_err | 0.970s | 286.122us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 1 | 100.00 | |||
| rv_timer_min | 0.560s | 33.686us | 1 | 1 | 100.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.600s | 179.487us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| rv_timer_stress_all_with_rand_reset | 10.930s | 4867.648us | 1 | 1 | 100.00 | |