Simulation Results: spi_device

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.33 %
  • code
  • 93.33 %
  • assert
  • 94.30 %
  • func
  • 74.36 %
  • line
  • 99.11 %
  • branch
  • 98.37 %
  • cond
  • 96.29 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 21.680s 4406.959us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.960s 21.322us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.610s 93.894us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 17.120s 3637.929us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.140s 115.114us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.440s 471.244us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.610s 93.894us 1 1 100.00
spi_device_csr_aliasing 5.140s 115.114us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 17.686us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.150s 65.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 41.418us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.630s 0.897us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.660s 6.583us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.750s 92.182us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.750s 92.182us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.650s 14.779us 1 1 100.00
spi_device_tpm_sts_read 0.770s 65.471us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 15.930s 4041.543us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.540s 2041.342us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.840s 240.524us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.840s 240.524us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 17.500s 2794.386us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 17.500s 2794.386us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 17.500s 2794.386us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 17.500s 2794.386us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 17.500s 2794.386us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.780s 771.297us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 20.910s 2586.117us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 20.910s 2586.117us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 20.910s 2586.117us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.020s 264.886us 1 1 100.00
spi_device_read_buffer_direct 9.980s 5389.774us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 20.910s 2586.117us 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 71.250s 167223.491us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.690s 13677.494us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.690s 13677.494us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 21.680s 4406.959us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 159.780s 107725.935us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 305.120s 91414.014us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.640s 30.015us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.660s 41.103us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.890s 135.113us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.890s 135.113us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 21.322us 1 1 100.00
spi_device_csr_rw 1.610s 93.894us 1 1 100.00
spi_device_csr_aliasing 5.140s 115.114us 1 1 100.00
spi_device_same_csr_outstanding 2.290s 447.478us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 21.322us 1 1 100.00
spi_device_csr_rw 1.610s 93.894us 1 1 100.00
spi_device_csr_aliasing 5.140s 115.114us 1 1 100.00
spi_device_same_csr_outstanding 2.290s 447.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.010s 116.409us 1 1 100.00
spi_device_tl_intg_err 8.250s 208.842us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.250s 208.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 14.030s 18312.735us 1 1 100.00