Simulation Results: sram_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.36 %
  • code
  • 95.53 %
  • assert
  • 95.55 %
  • func
  • 94.99 %
  • line
  • 98.84 %
  • branch
  • 96.53 %
  • cond
  • 91.55 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 15.090s 906.101us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.770s 30.929us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.770s 17.135us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.540s 144.221us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 23.544us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.720s 378.201us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.770s 17.135us 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 23.544us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 255.820s 42179.915us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 126.650s 15695.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 1243.520s 85462.657us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 135.730s 3215.129us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 684.670s 70753.280us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 435.830s 46654.862us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 40.400s 44838.993us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 409.020s 65223.156us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.950s 1261.188us 1 1 100.00
sram_ctrl_partial_access_b2b 179.900s 6662.956us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 21.250s 2894.237us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.580s 2568.667us 1 1 100.00
sram_ctrl_throughput_w_readback 24.270s 3189.122us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 316.150s 2424.447us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.720s 1169.771us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1324.050s 33475.409us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.690s 16.229us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.880s 37.723us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.880s 37.723us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.770s 30.929us 1 1 100.00
sram_ctrl_csr_rw 0.770s 17.135us 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 23.544us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.870s 15.166us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.770s 30.929us 1 1 100.00
sram_ctrl_csr_rw 0.770s 17.135us 1 1 100.00
sram_ctrl_csr_aliasing 0.780s 23.544us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.870s 15.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.800s 7366.777us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.010s 673.693us 1 1 100.00
sram_ctrl_sec_cm 0.810s 6.881us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.881us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.010s 673.693us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 316.150s 2424.447us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 316.150s 2424.447us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.770s 17.135us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 409.020s 65223.156us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 409.020s 65223.156us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 409.020s 65223.156us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 40.400s 44838.993us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.820s 670.257us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 29.800s 7366.777us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3.580s 1316.762us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 15.090s 906.101us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 15.090s 906.101us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 409.020s 65223.156us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.881us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 40.400s 44838.993us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.881us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.881us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 15.090s 906.101us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.810s 6.881us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.720s 289.742us 1 1 100.00