Simulation Results: sram_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.41 %
  • code
  • 96.02 %
  • assert
  • 95.79 %
  • func
  • 94.43 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.41 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.810s 135.316us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.780s 16.166us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.740s 15.768us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.320s 522.294us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 46.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.090s 132.576us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.740s 15.768us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 46.689us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.950s 449.357us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.900s 662.365us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 499.570s 10927.368us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 201.170s 2793.983us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 50.530s 3807.688us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 428.920s 4970.817us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.430s 755.228us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 667.390s 3070.061us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 52.330s 875.540us 1 1 100.00
sram_ctrl_partial_access_b2b 306.140s 95535.827us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 11.040s 318.566us 1 1 100.00
sram_ctrl_throughput_w_partial_write 11.280s 84.223us 1 1 100.00
sram_ctrl_throughput_w_readback 24.310s 433.434us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 911.620s 103012.548us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.760s 125.235us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 558.200s 53909.331us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.620s 35.374us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.890s 109.022us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.890s 109.022us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 16.166us 1 1 100.00
sram_ctrl_csr_rw 0.740s 15.768us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 46.689us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 52.773us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 16.166us 1 1 100.00
sram_ctrl_csr_rw 0.740s 15.768us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 46.689us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.710s 52.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.190s 941.679us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.310s 139.434us 1 1 100.00
sram_ctrl_sec_cm 0.750s 5.080us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.750s 5.080us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.310s 139.434us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 911.620s 103012.548us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 911.620s 103012.548us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.740s 15.768us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 667.390s 3070.061us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 667.390s 3070.061us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 667.390s 3070.061us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.430s 755.228us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.870s 38.672us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.190s 941.679us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.970s 361.032us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.810s 135.316us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.810s 135.316us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 667.390s 3070.061us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.750s 5.080us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.430s 755.228us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.750s 5.080us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.750s 5.080us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.810s 135.316us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.750s 5.080us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 27.760s 2232.729us 1 1 100.00