Simulation Results: sysrst_ctrl

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.95 %
  • code
  • 92.01 %
  • assert
  • 91.48 %
  • func
  • 62.35 %
  • line
  • 96.78 %
  • branch
  • 96.89 %
  • cond
  • 93.93 %
  • toggle
  • 100.00 %
  • FSM
  • 72.44 %
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.420s 2133.817us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.880s 2467.200us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.620s 2266.166us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.970s 2304.269us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 5.150s 6056.942us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.480s 2112.809us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 7.020s 11841.811us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.690s 2473.302us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.570s 2083.024us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.480s 2112.809us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.690s 2473.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 29.700s 61695.030us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 84.860s 104924.367us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.170s 3386.481us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.940s 2949.066us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.300s 2509.955us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.700s 2126.160us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.940s 3724.378us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.730s 2632.901us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 2.150s 4105.735us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 35.420s 36589.934us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 22.080s 11480.777us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.460s 2027.472us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.880s 2012.645us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.160s 2091.660us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.160s 2091.660us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.150s 6056.942us 1 1 100.00
sysrst_ctrl_csr_rw 1.480s 2112.809us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.690s 2473.302us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.960s 5049.830us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.150s 6056.942us 1 1 100.00
sysrst_ctrl_csr_rw 1.480s 2112.809us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.690s 2473.302us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.960s 5049.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 40.740s 22254.010us 1 1 100.00
sysrst_ctrl_sec_cm 17.310s 42272.143us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 40.740s 22254.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.850s 9660.998us 1 1 100.00