Simulation Results: uart

 
27/11/2025 16:30:45 sha: 8a15de8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.31 %
  • code
  • 95.90 %
  • assert
  • 97.12 %
  • func
  • 56.90 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.830s 851.328us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 22.707us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.550s 27.850us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.170s 136.293us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.680s 54.334us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.620s 66.789us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.550s 27.850us 1 1 100.00
uart_csr_aliasing 0.680s 54.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 49.810s 119069.477us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.830s 851.328us 1 1 100.00
uart_tx_rx 49.810s 119069.477us 1 1 100.00
parity_error 2 2 100.00
uart_intr 333.240s 281843.986us 1 1 100.00
uart_rx_parity_err 120.160s 130287.088us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 49.810s 119069.477us 1 1 100.00
uart_intr 333.240s 281843.986us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 85.640s 204614.595us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 40.350s 35162.499us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 76.580s 84953.602us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 333.240s 281843.986us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 333.240s 281843.986us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 333.240s 281843.986us 1 1 100.00
perf 1 1 100.00
uart_perf 174.680s 17797.490us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.070s 4397.462us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.070s 4397.462us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 11.210s 49936.118us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.810s 941.888us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.020s 9255.863us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 37.060s 5565.114us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 459.490s 110927.312us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 170.450s 112827.703us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.530s 13.843us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 28.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.210s 128.224us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.210s 128.224us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 22.707us 1 1 100.00
uart_csr_rw 0.550s 27.850us 1 1 100.00
uart_csr_aliasing 0.680s 54.334us 1 1 100.00
uart_same_csr_outstanding 0.600s 34.174us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 22.707us 1 1 100.00
uart_csr_rw 0.550s 27.850us 1 1 100.00
uart_csr_aliasing 0.680s 54.334us 1 1 100.00
uart_same_csr_outstanding 0.600s 34.174us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.770s 253.856us 1 1 100.00
uart_tl_intg_err 1.130s 71.332us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.130s 71.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 51.970s 22154.403us 1 1 100.00