Simulation Results: adc_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.64 %
  • code
  • 96.52 %
  • assert
  • 95.95 %
  • func
  • 49.46 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 95.70 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 6.190s 5705.592us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.630s 1093.185us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.780s 482.412us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 20.110s 17128.887us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.900s 1190.438us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.470s 422.598us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.780s 482.412us 1 1 100.00
adc_ctrl_csr_aliasing 2.900s 1190.438us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 404.530s 492769.685us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 502.460s 501465.772us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 250.730s 159853.137us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 299.020s 162414.575us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 435.410s 519138.628us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 88.040s 199724.198us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 401.400s 518144.728us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 192.740s 520777.561us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 10.750s 5657.466us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 86.400s 47701.052us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 145.740s 94438.291us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 69.970s 161276.287us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.770s 491.440us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.470s 425.365us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.440s 773.344us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.440s 773.344us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.630s 1093.185us 1 1 100.00
adc_ctrl_csr_rw 1.780s 482.412us 1 1 100.00
adc_ctrl_csr_aliasing 2.900s 1190.438us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.950s 4590.312us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.630s 1093.185us 1 1 100.00
adc_ctrl_csr_rw 1.780s 482.412us 1 1 100.00
adc_ctrl_csr_aliasing 2.900s 1190.438us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.950s 4590.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.550s 4276.552us 1 1 100.00
adc_ctrl_tl_intg_err 16.650s 8320.041us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 16.650s 8320.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 10.720s 8275.166us 1 1 100.00