Simulation Results: edn

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.18 %
  • code
  • 80.94 %
  • assert
  • 94.89 %
  • func
  • 76.72 %
  • line
  • 96.95 %
  • branch
  • 89.44 %
  • cond
  • 84.62 %
  • toggle
  • 81.34 %
  • FSM
  • 52.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 47.464us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.970s 12.464us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.030s 23.817us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.310s 384.782us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.380s 107.130us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.450s 81.314us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.030s 23.817us 1 1 100.00
edn_csr_aliasing 1.380s 107.130us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.870s 95.581us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.870s 95.581us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.870s 95.581us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.890s 32.602us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 66.275us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 18.930us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 34.874us 1 1 100.00
edn_disable_auto_req_mode 1.130s 123.803us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.130s 391.431us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 34.463us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 60.849us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.190s 565.799us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.190s 565.799us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.970s 12.464us 1 1 100.00
edn_csr_rw 1.030s 23.817us 1 1 100.00
edn_csr_aliasing 1.380s 107.130us 1 1 100.00
edn_same_csr_outstanding 1.100s 16.424us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.970s 12.464us 1 1 100.00
edn_csr_rw 1.030s 23.817us 1 1 100.00
edn_csr_aliasing 1.380s 107.130us 1 1 100.00
edn_same_csr_outstanding 1.100s 16.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.520s 886.720us 1 1 100.00
edn_tl_intg_err 1.840s 79.868us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 29.704us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 66.275us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.520s 886.720us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.520s 886.720us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.520s 886.720us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.520s 886.720us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 66.275us 1 1 100.00
edn_sec_cm 3.520s 886.720us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 66.275us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.840s 79.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 16.480s 6760.476us 1 1 100.00