Simulation Results: flash_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.54 %
  • code
  • 94.29 %
  • assert
  • 96.62 %
  • func
  • 95.70 %
  • line
  • 95.93 %
  • branch
  • 97.15 %
  • cond
  • 93.77 %
  • toggle
  • 97.51 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.46%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 40.700s 178.070us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.870s 18.463us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 21.540s 350.582us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 29.520s 4075.212us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 27.450s 431.108us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 13.080s 140.621us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
flash_ctrl_csr_aliasing 27.450s 431.108us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 8.460s 72.966us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.010s 19.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.930s 84.635us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 34.310s 791.752us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1168.200s 83858.109us 1 1 100.00
flash_ctrl_hw_rma_reset 548.250s 40130.039us 1 1 100.00
flash_ctrl_lcmgr_intg 7.900s 73.250us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1750.700s 266899.946us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 242.080s 6571.900us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 9.640s 67.212us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1887.080s 156515.313us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 58.880s 1443.770us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.280s 29.703us 1 1 100.00
flash_ctrl_rw_evict_all_en 11.910s 72.891us 1 1 100.00
flash_ctrl_re_evict 18.120s 73.738us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 59.940s 62.668us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 59.940s 62.668us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 622.320s 24513.169us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 25.050s 2301.870us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 369.740s 1648.613us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 419.880s 17409.767us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 285.710s 568.692us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 776.540s 3143.485us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.430s 41.674us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 152.870s 5900.016us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.910s 40.543us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.990s 17.598us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 316.610s 1170.068us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 38.060s 6091.805us 1 1 100.00
flash_ctrl_otp_reset 63.230s 42.809us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1168.200s 83858.109us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 124.760s 1754.563us 1 1 100.00
flash_ctrl_intr_wr 48.750s 5501.848us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 337.270s 165564.977us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 121.050s 33740.722us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 36.840s 1470.256us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 40.970s 827.314us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.320s 44.880us 1 1 100.00
flash_ctrl_ro_derr 109.440s 2349.620us 1 1 100.00
flash_ctrl_rw_derr 132.370s 8550.524us 1 1 100.00
flash_ctrl_derr_detect 94.800s 1620.422us 1 1 100.00
flash_ctrl_integrity 429.740s 18105.287us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 18.660s 26.466us 1 1 100.00
flash_ctrl_ro_serr 90.070s 696.924us 1 1 100.00
flash_ctrl_rw_serr 152.650s 2129.220us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 48.260s 2523.253us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 34.210s 568.546us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 129.280s 8973.453us 1 1 100.00
flash_ctrl_write_word_sweep 13.340s 304.309us 1 1 100.00
flash_ctrl_read_word_sweep 9.930s 23.806us 1 1 100.00
flash_ctrl_ro 67.210s 634.143us 1 1 100.00
flash_ctrl_rw 0.000s 0.000us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.060s 667.341us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 682.920s 159323.558us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 35.800s 10066.027us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.500s 29.359us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.400s 46.818us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.850s 43.961us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.850s 43.961us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.540s 350.582us 1 1 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
flash_ctrl_csr_aliasing 27.450s 431.108us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.710s 62.015us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.540s 350.582us 1 1 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
flash_ctrl_csr_aliasing 27.450s 431.108us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.710s 62.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 16.270s 1006.613us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 369.870s 759.329us 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 369.870s 759.329us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 369.870s 759.329us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.950s 217.306us 1 1 100.00
flash_ctrl_wr_intg 13.580s 171.426us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 40.700s 178.070us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 63.230s 42.809us 1 1 100.00
flash_ctrl_disable 9.910s 40.543us 1 1 100.00
flash_ctrl_sec_info_access 36.110s 3555.305us 1 1 100.00
flash_ctrl_connect 6.990s 17.598us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.440s 21.722us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.240s 128.043us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 51.600s 156.414us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.910s 40.543us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.950s 217.306us 1 1 100.00
flash_ctrl_access_after_disable 5.610s 111.104us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 23.390s 125.103us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.910s 40.543us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 25.050s 2301.870us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 0.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 152.650s 2129.220us 1 1 100.00
flash_ctrl_rw_derr 132.370s 8550.524us 1 1 100.00
flash_ctrl_integrity 429.740s 18105.287us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1168.200s 83858.109us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.470s 918.772us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.600s 39.343us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.310s 25.126us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1449.980s 1842.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.300s 128.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 180.050s 274.035us 1 1 100.00