Simulation Results: hmac

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.12 %
  • code
  • 97.10 %
  • assert
  • 96.90 %
  • func
  • 43.37 %
  • line
  • 99.58 %
  • branch
  • 99.01 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.440s 709.377us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 114.786us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.960s 34.866us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.970s 3274.775us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.980s 1420.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.740s 232.627us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.960s 34.866us 1 1 100.00
hmac_csr_aliasing 3.980s 1420.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 22.520s 2848.317us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 43.510s 1050.261us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 193.540s 13674.000us 1 1 100.00
hmac_test_sha384_vectors 19.440s 215.880us 1 1 100.00
hmac_test_sha512_vectors 19.090s 221.770us 1 1 100.00
hmac_test_hmac256_vectors 6.720s 851.008us 1 1 100.00
hmac_test_hmac384_vectors 8.980s 310.146us 1 1 100.00
hmac_test_hmac512_vectors 11.110s 1298.878us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.470s 6109.894us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 570.820s 28281.959us 1 1 100.00
error 1 1 100.00
hmac_error 10.330s 549.790us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 6.710s 2805.469us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.440s 709.377us 1 1 100.00
hmac_long_msg 22.520s 2848.317us 1 1 100.00
hmac_back_pressure 43.510s 1050.261us 1 1 100.00
hmac_datapath_stress 570.820s 28281.959us 1 1 100.00
hmac_burst_wr 7.470s 6109.894us 1 1 100.00
hmac_stress_all 43.750s 12216.515us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.440s 709.377us 1 1 100.00
hmac_long_msg 22.520s 2848.317us 1 1 100.00
hmac_back_pressure 43.510s 1050.261us 1 1 100.00
hmac_datapath_stress 570.820s 28281.959us 1 1 100.00
hmac_wipe_secret 6.710s 2805.469us 1 1 100.00
hmac_test_sha256_vectors 193.540s 13674.000us 1 1 100.00
hmac_test_sha384_vectors 19.440s 215.880us 1 1 100.00
hmac_test_sha512_vectors 19.090s 221.770us 1 1 100.00
hmac_test_hmac256_vectors 6.720s 851.008us 1 1 100.00
hmac_test_hmac384_vectors 8.980s 310.146us 1 1 100.00
hmac_test_hmac512_vectors 11.110s 1298.878us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.440s 709.377us 1 1 100.00
hmac_long_msg 22.520s 2848.317us 1 1 100.00
hmac_back_pressure 43.510s 1050.261us 1 1 100.00
hmac_datapath_stress 570.820s 28281.959us 1 1 100.00
hmac_burst_wr 7.470s 6109.894us 1 1 100.00
hmac_error 10.330s 549.790us 1 1 100.00
hmac_wipe_secret 6.710s 2805.469us 1 1 100.00
hmac_test_sha256_vectors 193.540s 13674.000us 1 1 100.00
hmac_test_sha384_vectors 19.440s 215.880us 1 1 100.00
hmac_test_sha512_vectors 19.090s 221.770us 1 1 100.00
hmac_test_hmac256_vectors 6.720s 851.008us 1 1 100.00
hmac_test_hmac384_vectors 8.980s 310.146us 1 1 100.00
hmac_test_hmac512_vectors 11.110s 1298.878us 1 1 100.00
hmac_stress_all 43.750s 12216.515us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 43.750s 12216.515us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.560s 15.946us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 22.411us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.030s 216.381us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.030s 216.381us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 114.786us 1 1 100.00
hmac_csr_rw 0.960s 34.866us 1 1 100.00
hmac_csr_aliasing 3.980s 1420.918us 1 1 100.00
hmac_same_csr_outstanding 1.400s 122.989us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 114.786us 1 1 100.00
hmac_csr_rw 0.960s 34.866us 1 1 100.00
hmac_csr_aliasing 3.980s 1420.918us 1 1 100.00
hmac_same_csr_outstanding 1.400s 122.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.990s 555.166us 1 1 100.00
hmac_sec_cm 1.010s 91.583us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.990s 555.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.440s 709.377us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.860s 112.772us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 168.600s 10057.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.050s 24.159us 1 1 100.00