Simulation Results: lc_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.57 %
  • code
  • 84.38 %
  • assert
  • 94.13 %
  • func
  • 90.21 %
  • line
  • 97.04 %
  • branch
  • 93.82 %
  • cond
  • 79.45 %
  • toggle
  • 81.39 %
  • FSM
  • 70.21 %
Validation stages
V1
100.00%
V2
92.50%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.570s 70.349us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.850s 15.795us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.960s 16.101us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.090s 109.764us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 22.510us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.790s 67.686us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.960s 16.101us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 22.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.800s 643.976us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.460s 1100.580us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.690s 11.711us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.080s 66.165us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.360s 621.065us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_prog_failure 2.080s 66.165us 1 1 100.00
lc_ctrl_errors 6.360s 621.065us 1 1 100.00
lc_ctrl_security_escalation 5.400s 468.518us 1 1 100.00
lc_ctrl_jtag_state_failure 7.110s 652.082us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.440s 254.072us 1 1 100.00
lc_ctrl_jtag_errors 45.940s 16420.246us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.670s 462.797us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.250s 407.354us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.440s 254.072us 1 1 100.00
lc_ctrl_jtag_errors 45.940s 16420.246us 1 1 100.00
lc_ctrl_jtag_access 3.010s 1119.504us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.980s 789.873us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.440s 324.630us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.520s 267.543us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.940s 1772.274us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.140s 926.998us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.970s 21.289us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.010s 200.623us 1 1 100.00
lc_ctrl_jtag_alert_test 1.160s 493.614us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.490s 268.030us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.880s 28.434us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 6.220s 604.651us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.830s 70.861us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.930s 44.933us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.930s 44.933us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 15.795us 1 1 100.00
lc_ctrl_csr_rw 0.960s 16.101us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 22.510us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.370s 86.474us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 15.795us 1 1 100.00
lc_ctrl_csr_rw 0.960s 16.101us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 22.510us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.370s 86.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 238.469us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 238.469us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.460s 1100.580us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.160s 30.372us 0 1 0.00
lc_ctrl_sec_cm 6.970s 231.123us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.400s 468.518us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.800s 643.976us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.250s 407.354us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.040s 297.884us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.040s 297.884us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.410s 761.285us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.190s 1195.568us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.190s 1195.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 37.380s 11511.405us 0 1 0.00