Simulation Results: lc_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 83.13 %
  • assert
  • 93.85 %
  • func
  • 89.86 %
  • line
  • 96.97 %
  • branch
  • 93.18 %
  • cond
  • 79.14 %
  • toggle
  • 76.89 %
  • FSM
  • 69.47 %
Validation stages
V1
100.00%
V2
90.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.370s 165.236us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 15.440us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 19.252us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 66.116us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 21.517us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 114.181us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 19.252us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 21.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.910s 46.372us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.980s 1076.021us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 14.868us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.120s 292.800us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.740s 1103.013us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_prog_failure 2.120s 292.800us 1 1 100.00
lc_ctrl_errors 5.740s 1103.013us 1 1 100.00
lc_ctrl_security_escalation 7.550s 388.213us 1 1 100.00
lc_ctrl_jtag_state_failure 16.340s 5619.468us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.810s 223.783us 1 1 100.00
lc_ctrl_jtag_errors 19.430s 2256.398us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 5.100s 265.183us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.310s 590.184us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.810s 223.783us 1 1 100.00
lc_ctrl_jtag_errors 19.430s 2256.398us 1 1 100.00
lc_ctrl_jtag_access 1.110s 322.728us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.370s 1708.533us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.060s 98.693us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.370s 48.608us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.850s 765.926us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.150s 506.379us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.390s 42.827us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.450s 606.984us 1 1 100.00
lc_ctrl_jtag_alert_test 1.200s 206.716us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.590s 5900.482us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 19.720us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 22.400s 5170.559us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 125.252us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.490s 133.855us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.490s 133.855us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 15.440us 1 1 100.00
lc_ctrl_csr_rw 0.930s 19.252us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 21.517us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.300s 67.988us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 15.440us 1 1 100.00
lc_ctrl_csr_rw 0.930s 19.252us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 21.517us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.300s 67.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
lc_ctrl_tl_intg_err 1.690s 66.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.690s 66.387us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.980s 1076.021us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.130s 112.959us 0 1 0.00
lc_ctrl_sec_cm 5.610s 1994.268us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.550s 388.213us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.910s 46.372us 0 1 0.00
lc_ctrl_jtag_state_post_trans 2.310s 590.184us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.150s 817.071us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.150s 817.071us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.570s 692.243us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 12.730s 3737.547us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 12.730s 3737.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.860s 374.049us 0 1 0.00