Simulation Results: pwrmgr

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.79 %
  • code
  • 94.43 %
  • assert
  • 96.08 %
  • func
  • 96.87 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 93.78 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.840s 22.123us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.620s 30.352us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 20.263us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.430s 113.186us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.760s 56.517us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.080s 96.269us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 20.263us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 56.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.020s 198.627us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.020s 198.627us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.870s 128.156us 1 1 100.00
pwrmgr_lowpower_invalid 0.820s 39.147us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.630s 55.733us 1 1 100.00
pwrmgr_reset_invalid 0.740s 114.771us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.630s 55.733us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.100s 398.006us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.610s 26.509us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.970s 135.102us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.300s 1088.479us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 16.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.860s 413.239us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.860s 413.239us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 30.352us 1 1 100.00
pwrmgr_csr_rw 0.630s 20.263us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 56.517us 1 1 100.00
pwrmgr_same_csr_outstanding 0.890s 30.979us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.620s 30.352us 1 1 100.00
pwrmgr_csr_rw 0.630s 20.263us 1 1 100.00
pwrmgr_csr_aliasing 0.760s 56.517us 1 1 100.00
pwrmgr_same_csr_outstanding 0.890s 30.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.690s 7.384us 0 1 0.00
pwrmgr_sec_cm 0.670s 28.753us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.670s 28.753us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.670s 28.753us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.690s 7.384us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.600s 1617.552us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.100s 398.006us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.790s 89.501us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.730s 40.591us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.670s 28.753us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.670s 28.753us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.670s 28.753us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.640s 35.385us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.570s 35.413us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 182.390us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 20.263us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 20.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.680s 341.736us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 11.920s 13897.407us 0 1 0.00