Simulation Results: rom_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.06 %
  • code
  • 96.67 %
  • assert
  • 95.34 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 97.81 %
  • cond
  • 93.31 %
  • toggle
  • 99.44 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.020s 263.937us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.770s 306.368us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.320s 555.076us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.940s 182.869us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 2100.891us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.300s 136.629us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.320s 555.076us 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 2100.891us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.110s 791.544us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.440s 210.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.050s 395.956us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.690s 3073.326us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.520s 420.360us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.110s 549.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.180s 2101.795us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.180s 2101.795us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.770s 306.368us 1 1 100.00
rom_ctrl_csr_rw 4.320s 555.076us 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 2100.891us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.740s 221.069us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.770s 306.368us 1 1 100.00
rom_ctrl_csr_rw 4.320s 555.076us 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 2100.891us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.740s 221.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.710s 11995.449us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 213.190s 1372.593us 0 1 0.00
rom_ctrl_tl_intg_err 24.110s 240.356us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 213.190s 1372.593us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 213.190s 1372.593us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 213.190s 1372.593us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 213.190s 1372.593us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.020s 263.937us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.020s 263.937us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.020s 263.937us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.110s 240.356us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
rom_ctrl_kmac_err_chk 7.520s 420.360us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 37.830s 1240.283us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.710s 11995.449us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 213.190s 1372.593us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 200.000s 6157.430us 1 1 100.00