Simulation Results: rom_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.27 %
  • code
  • 95.47 %
  • assert
  • 95.34 %
  • func
  • 94.99 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 94.21 %
  • toggle
  • 98.96 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.530s 1103.183us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.280s 1040.490us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.470s 657.998us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 9.860s 288.649us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.330s 209.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.310s 388.902us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.470s 657.998us 1 1 100.00
rom_ctrl_csr_aliasing 7.330s 209.978us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 9.530s 2124.712us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.610s 729.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.030s 394.527us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 23.650s 1515.272us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.810s 1368.724us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.680s 300.113us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.520s 1219.221us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.520s 1219.221us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.280s 1040.490us 1 1 100.00
rom_ctrl_csr_rw 7.470s 657.998us 1 1 100.00
rom_ctrl_csr_aliasing 7.330s 209.978us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.900s 544.794us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.280s 1040.490us 1 1 100.00
rom_ctrl_csr_rw 7.470s 657.998us 1 1 100.00
rom_ctrl_csr_aliasing 7.330s 209.978us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.900s 544.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.540s 3030.383us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_tl_intg_err 49.760s 450.742us 1 1 100.00
rom_ctrl_sec_cm 450.440s 1245.489us 0 1 0.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 450.440s 1245.489us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 450.440s 1245.489us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 450.440s 1245.489us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 450.440s 1245.489us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.530s 1103.183us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.530s 1103.183us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.530s 1103.183us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 49.760s 450.742us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
rom_ctrl_kmac_err_chk 11.810s 1368.724us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 84.910s 3829.716us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.540s 3030.383us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 450.440s 1245.489us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 143.830s 10596.193us 1 1 100.00