Simulation Results: rstmgr

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.78 %
  • code
  • 99.44 %
  • assert
  • 98.13 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.58 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.290s 243.707us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.770s 123.534us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.760s 70.157us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.050s 2269.672us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.420s 249.442us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.080s 138.397us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.760s 70.157us 1 1 100.00
rstmgr_csr_aliasing 1.420s 249.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.850s 133.364us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.060s 533.252us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.880s 115.082us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 2.890s 773.614us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 2.890s 773.614us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 2.890s 773.614us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 2.890s 773.614us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.740s 394.077us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.910s 69.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.910s 529.584us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.910s 529.584us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.770s 123.534us 1 1 100.00
rstmgr_csr_rw 0.760s 70.157us 1 1 100.00
rstmgr_csr_aliasing 1.420s 249.442us 1 1 100.00
rstmgr_same_csr_outstanding 1.260s 127.662us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.770s 123.534us 1 1 100.00
rstmgr_csr_rw 0.760s 70.157us 1 1 100.00
rstmgr_csr_aliasing 1.420s 249.442us 1 1 100.00
rstmgr_same_csr_outstanding 1.260s 127.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.610s 8593.187us 1 1 100.00
rstmgr_tl_intg_err 1.840s 454.073us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.610s 8593.187us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.610s 8593.187us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.840s 454.073us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.910s 150.825us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.920s 1968.371us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.050s 301.702us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.610s 8593.187us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 70.157us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 70.157us 1 1 100.00