Simulation Results: spi_device

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.68 %
  • code
  • 93.25 %
  • assert
  • 94.30 %
  • func
  • 69.49 %
  • line
  • 99.11 %
  • branch
  • 98.37 %
  • cond
  • 95.87 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 114.090s 12059.382us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.950s 15.645us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.080s 25.541us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.430s 622.169us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.230s 946.961us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.090s 36.352us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.080s 25.541us 1 1 100.00
spi_device_csr_aliasing 14.230s 946.961us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.950s 19.260us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.160s 58.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.830s 48.470us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.850s 1.326us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.870s 3.159us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.200s 91.294us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.200s 91.294us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.870s 4307.451us 1 1 100.00
spi_device_tpm_sts_read 0.860s 16.506us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 23.840s 6322.245us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.700s 2248.783us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.410s 408.510us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.410s 408.510us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.420s 1468.862us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.420s 1468.862us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.420s 1468.862us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.420s 1468.862us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.420s 1468.862us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.010s 1122.780us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 30.580s 7884.867us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 30.580s 7884.867us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 30.580s 7884.867us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 34.880s 4425.423us 1 1 100.00
spi_device_read_buffer_direct 5.980s 625.724us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 30.580s 7884.867us 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 4.210s 1837.972us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.800s 539.805us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.800s 539.805us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 114.090s 12059.382us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 70.220s 38259.286us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.230s 79.049us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.760s 16.241us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.620s 37.030us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.500s 506.399us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.500s 506.399us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.950s 15.645us 1 1 100.00
spi_device_csr_rw 1.080s 25.541us 1 1 100.00
spi_device_csr_aliasing 14.230s 946.961us 1 1 100.00
spi_device_same_csr_outstanding 3.180s 707.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.950s 15.645us 1 1 100.00
spi_device_csr_rw 1.080s 25.541us 1 1 100.00
spi_device_csr_aliasing 14.230s 946.961us 1 1 100.00
spi_device_same_csr_outstanding 3.180s 707.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 5.670s 280.849us 1 1 100.00
spi_device_sec_cm 1.340s 140.448us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.670s 280.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 21.170s 12383.807us 1 1 100.00