| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_host_smoke | 80.000s | 2321.840us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_hw_reset | 2.000s | 21.172us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_host_csr_rw | 1.000s | 58.541us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_host_csr_bit_bash | 3.000s | 55.363us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_host_csr_aliasing | 1.000s | 216.367us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_mem_rw_with_rand_reset | 2.000s | 38.188us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_host_csr_rw | 1.000s | 58.541us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 1.000s | 216.367us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_host_mem_walk | 1.000s | 23.501us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_host_mem_partial_access | 1.000s | 118.817us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| performance | 1 | 1 | 100.00 | |||
| spi_host_performance | 8.000s | 37.225us | 1 | 1 | 100.00 | |
| error_event_intr | 3 | 3 | 100.00 | |||
| spi_host_overflow_underflow | 6.000s | 251.245us | 1 | 1 | 100.00 | |
| spi_host_error_cmd | 4.000s | 20.873us | 1 | 1 | 100.00 | |
| spi_host_event | 220.000s | 55983.280us | 1 | 1 | 100.00 | |
| clock_rate | 1 | 1 | 100.00 | |||
| spi_host_speed | 12.000s | 124.914us | 1 | 1 | 100.00 | |
| speed | 1 | 1 | 100.00 | |||
| spi_host_speed | 12.000s | 124.914us | 1 | 1 | 100.00 | |
| chip_select_timing | 1 | 1 | 100.00 | |||
| spi_host_speed | 12.000s | 124.914us | 1 | 1 | 100.00 | |
| sw_reset | 1 | 1 | 100.00 | |||
| spi_host_sw_reset | 8.000s | 53.404us | 1 | 1 | 100.00 | |
| passthrough_mode | 1 | 1 | 100.00 | |||
| spi_host_passthrough_mode | 2.000s | 146.905us | 1 | 1 | 100.00 | |
| cpol_cpha | 1 | 1 | 100.00 | |||
| spi_host_speed | 12.000s | 124.914us | 1 | 1 | 100.00 | |
| full_cycle | 1 | 1 | 100.00 | |||
| spi_host_speed | 12.000s | 124.914us | 1 | 1 | 100.00 | |
| duplex | 1 | 1 | 100.00 | |||
| spi_host_smoke | 80.000s | 2321.840us | 1 | 1 | 100.00 | |
| tx_rx_only | 1 | 1 | 100.00 | |||
| spi_host_smoke | 80.000s | 2321.840us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_host_stress_all | 42.000s | 5154.633us | 1 | 1 | 100.00 | |
| spien | 1 | 1 | 100.00 | |||
| spi_host_spien | 2.000s | 171.124us | 1 | 1 | 100.00 | |
| stall | 1 | 1 | 100.00 | |||
| spi_host_status_stall | 15.000s | 1482.086us | 1 | 1 | 100.00 | |
| Idlecsbactive | 1 | 1 | 100.00 | |||
| spi_host_idlecsbactive | 3.000s | 395.128us | 1 | 1 | 100.00 | |
| data_fifo_status | 1 | 1 | 100.00 | |||
| spi_host_overflow_underflow | 6.000s | 251.245us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_host_alert_test | 1.000s | 16.869us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_host_intr_test | 1.000s | 19.568us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 2.000s | 156.965us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 2.000s | 156.965us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 2.000s | 21.172us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 1.000s | 58.541us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 1.000s | 216.367us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 2.000s | 39.540us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 2.000s | 21.172us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 1.000s | 58.541us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 1.000s | 216.367us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 2.000s | 39.540us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_host_sec_cm | 2.000s | 66.452us | 1 | 1 | 100.00 | |
| spi_host_tl_intg_err | 2.000s | 385.182us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_host_tl_intg_err | 2.000s | 385.182us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_host_upper_range_clkdiv | 114.000s | 10389.796us | 1 | 1 | 100.00 | |