Simulation Results: sram_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.14 %
  • code
  • 96.00 %
  • assert
  • 95.55 %
  • func
  • 93.88 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.66 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 16.980s 3453.136us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.650s 73.261us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.730s 98.679us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.210s 382.791us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 18.050us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.100s 1047.972us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.730s 98.679us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 18.050us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 88.410s 1980.259us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 59.630s 11425.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 612.130s 216005.686us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 171.440s 3705.240us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 971.340s 82924.357us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 255.530s 25391.669us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 37.340s 35283.517us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 626.010s 7959.090us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 17.820s 1079.031us 1 1 100.00
sram_ctrl_partial_access_b2b 311.880s 59105.790us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 14.320s 2990.639us 1 1 100.00
sram_ctrl_throughput_w_partial_write 22.540s 745.363us 1 1 100.00
sram_ctrl_throughput_w_readback 45.740s 3796.912us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 231.740s 36150.405us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.920s 353.079us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 5978.330s 3124381.613us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.600s 82.318us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.590s 444.373us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.590s 444.373us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.650s 73.261us 1 1 100.00
sram_ctrl_csr_rw 0.730s 98.679us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 18.050us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 27.693us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.650s 73.261us 1 1 100.00
sram_ctrl_csr_rw 0.730s 98.679us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 18.050us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 27.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.650s 3808.558us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.650s 1.708us 0 1 0.00
sram_ctrl_tl_intg_err 1.260s 95.673us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.650s 1.708us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.260s 95.673us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 231.740s 36150.405us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 231.740s 36150.405us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.730s 98.679us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 626.010s 7959.090us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 626.010s 7959.090us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 626.010s 7959.090us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 37.340s 35283.517us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.460s 695.278us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.650s 3808.558us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.480s 1335.035us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 16.980s 3453.136us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 16.980s 3453.136us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 626.010s 7959.090us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.650s 1.708us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 37.340s 35283.517us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.650s 1.708us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 1.708us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 16.980s 3453.136us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.650s 1.708us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 100.050s 2789.550us 1 1 100.00