Simulation Results: sram_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.76 %
  • code
  • 93.60 %
  • assert
  • 95.51 %
  • func
  • 95.18 %
  • line
  • 98.51 %
  • branch
  • 96.46 %
  • cond
  • 92.29 %
  • toggle
  • 90.25 %
  • FSM
  • 90.48 %
Validation stages
V1
90.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 11.750s 798.623us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.640s 22.052us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.710s 181.437us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.880s 728.331us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.242us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.210s 657.736us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.710s 181.437us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.242us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.850s 3334.820us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.900s 302.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 428.550s 14808.984us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 186.500s 10525.369us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 22.540s 6921.363us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 419.150s 37953.561us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.590s 2478.200us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 258.390s 3071.708us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.740s 94.946us 1 1 100.00
sram_ctrl_partial_access_b2b 177.070s 13889.461us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 45.880s 540.591us 1 1 100.00
sram_ctrl_throughput_w_partial_write 22.900s 450.660us 1 1 100.00
sram_ctrl_throughput_w_readback 7.140s 126.309us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 570.110s 129268.387us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.680s 28.096us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 272.960s 16105.995us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.610s 21.372us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.800s 51.780us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.800s 51.780us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 22.052us 1 1 100.00
sram_ctrl_csr_rw 0.710s 181.437us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.242us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 41.567us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.640s 22.052us 1 1 100.00
sram_ctrl_csr_rw 0.710s 181.437us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 18.242us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.680s 41.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.850s 1639.613us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.740s 11.810us 0 1 0.00
sram_ctrl_tl_intg_err 1.280s 807.774us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.740s 11.810us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.280s 807.774us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 570.110s 129268.387us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 570.110s 129268.387us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.710s 181.437us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 258.390s 3071.708us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 258.390s 3071.708us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 258.390s 3071.708us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.590s 2478.200us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.960s 53.711us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.850s 1639.613us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.900s 405.008us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 11.750s 798.623us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 11.750s 798.623us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 258.390s 3071.708us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.740s 11.810us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.590s 2478.200us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.740s 11.810us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.740s 11.810us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 11.750s 798.623us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.740s 11.810us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 353.180s 7063.360us 1 1 100.00