Simulation Results: sysrst_ctrl

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.20 %
  • code
  • 90.22 %
  • assert
  • 89.18 %
  • func
  • 67.21 %
  • line
  • 95.78 %
  • branch
  • 96.33 %
  • cond
  • 93.62 %
  • toggle
  • 100.00 %
  • FSM
  • 65.38 %
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.800s 2124.247us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.870s 2488.040us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.300s 2400.389us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.390s 2274.477us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 13.360s 6019.007us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.440s 2040.099us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 21.970s 21252.122us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.690s 2144.400us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.220s 2253.767us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.440s 2040.099us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.690s 2144.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 234.700s 116977.961us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 67.360s 65923.732us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 7.260s 3060.042us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.930s 3337.446us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.110s 2535.627us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.030s 2169.668us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.510s 4265.608us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.160s 2709.866us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 3.040s 4685.826us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 62.210s 34303.835us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.020s 11361.616us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.820s 2011.276us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.510s 2021.360us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.110s 2178.653us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.110s 2178.653us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 13.360s 6019.007us 1 1 100.00
sysrst_ctrl_csr_rw 4.440s 2040.099us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.690s 2144.400us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.790s 4549.881us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 13.360s 6019.007us 1 1 100.00
sysrst_ctrl_csr_rw 4.440s 2040.099us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.690s 2144.400us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.790s 4549.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 7.860s 22760.205us 1 1 100.00
sysrst_ctrl_sec_cm 34.680s 42046.783us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 7.860s 22760.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 2.890s 5480.883us 1 1 100.00