Simulation Results: uart

 
01/12/2025 17:24:06 sha: a49b553 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.89 %
  • code
  • 96.02 %
  • assert
  • 97.12 %
  • func
  • 49.54 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.38 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.760s 621.926us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.780s 73.755us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 39.246us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.460s 116.112us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.860s 103.011us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.800s 25.357us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 39.246us 1 1 100.00
uart_csr_aliasing 0.860s 103.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.910s 30609.661us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.760s 621.926us 1 1 100.00
uart_tx_rx 9.910s 30609.661us 1 1 100.00
parity_error 2 2 100.00
uart_intr 11.670s 18192.512us 1 1 100.00
uart_rx_parity_err 4.020s 9825.646us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.910s 30609.661us 1 1 100.00
uart_intr 11.670s 18192.512us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 38.270s 35775.207us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 16.030s 12555.126us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 11.370s 134895.916us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 11.670s 18192.512us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 11.670s 18192.512us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 11.670s 18192.512us 1 1 100.00
perf 1 1 100.00
uart_perf 71.230s 7788.433us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.540s 1431.375us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.540s 1431.375us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.230s 571.947us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.010s 3468.868us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 15.420s 7112.307us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 20.820s 6494.638us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 165.590s 176784.077us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 45.590s 132631.337us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 44.934us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.760s 30.507us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.310s 28.548us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.310s 28.548us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.780s 73.755us 1 1 100.00
uart_csr_rw 0.580s 39.246us 1 1 100.00
uart_csr_aliasing 0.860s 103.011us 1 1 100.00
uart_same_csr_outstanding 0.810s 54.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.780s 73.755us 1 1 100.00
uart_csr_rw 0.580s 39.246us 1 1 100.00
uart_csr_aliasing 0.860s 103.011us 1 1 100.00
uart_same_csr_outstanding 0.810s 54.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.070s 1431.232us 1 1 100.00
uart_tl_intg_err 1.270s 79.218us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.270s 79.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 9.650s 2401.768us 1 1 100.00