Simulation Results: adc_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.40 %
  • code
  • 96.42 %
  • assert
  • 95.95 %
  • func
  • 45.82 %
  • line
  • 99.02 %
  • branch
  • 98.58 %
  • cond
  • 95.29 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.910s 5805.130us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.100s 1110.191us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.310s 515.293us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 31.820s 40501.260us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.530s 1344.652us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.120s 641.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.310s 515.293us 1 1 100.00
adc_ctrl_csr_aliasing 2.530s 1344.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 51.200s 497517.980us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 207.380s 487698.336us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 171.140s 498084.921us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 46.790s 168643.261us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 36.010s 369460.994us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 81.060s 197108.227us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 315.640s 165771.061us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 489.190s 326192.610us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 8.020s 4476.969us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 60.780s 36812.970us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 62.230s 73608.467us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 277.920s 170582.817us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.650s 298.938us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.150s 511.872us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 3.790s 628.258us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 3.790s 628.258us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.100s 1110.191us 1 1 100.00
adc_ctrl_csr_rw 1.310s 515.293us 1 1 100.00
adc_ctrl_csr_aliasing 2.530s 1344.652us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.330s 4499.821us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.100s 1110.191us 1 1 100.00
adc_ctrl_csr_rw 1.310s 515.293us 1 1 100.00
adc_ctrl_csr_aliasing 2.530s 1344.652us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.330s 4499.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 8.910s 8098.733us 1 1 100.00
adc_ctrl_sec_cm 9.310s 3472.682us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.910s 8098.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 13.130s 11303.512us 1 1 100.00