| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
33.33% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| aon_timer_smoke | 0.930s | 580.554us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.350s | 1272.322us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aon_timer_csr_rw | 0.750s | 357.908us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 3.760s | 7208.271us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 1.190s | 565.422us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 0.940s | 596.405us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aon_timer_csr_rw | 0.750s | 357.908us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.190s | 565.422us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 0.800s | 433.480us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 0.840s | 391.441us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 1 | 1 | 100.00 | |||
| aon_timer_prescaler | 1.720s | 8844.998us | 1 | 1 | 100.00 | |
| jump | 1 | 1 | 100.00 | |||
| aon_timer_jump | 1.030s | 635.243us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aon_timer_stress_all | 22.660s | 87463.900us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aon_timer_alert_test | 1.120s | 439.215us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| aon_timer_intr_test | 0.980s | 290.744us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 1.360s | 579.054us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 1.360s | 579.054us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.350s | 1272.322us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 0.750s | 357.908us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.190s | 565.422us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 1.630s | 937.633us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.350s | 1272.322us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 0.750s | 357.908us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.190s | 565.422us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 1.630s | 937.633us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| aon_timer_sec_cm | 3.430s | 8282.865us | 1 | 1 | 100.00 | |
| aon_timer_tl_intg_err | 1.130s | 426.783us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| aon_timer_tl_intg_err | 1.130s | 426.783us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_max_thold | 0.910s | 691.010us | 1 | 1 | 100.00 | |
| min_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_min_thold | 0.820s | 577.526us | 1 | 1 | 100.00 | |
| wkup_count_hi_cdc | 1 | 1 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 7.080s | 4289.681us | 1 | 1 | 100.00 | |
| custom_intr | 1 | 1 | 100.00 | |||
| aon_timer_custom_intr | 0.830s | 739.192us | 1 | 1 | 100.00 | |
| alternating_on_off | 1 | 1 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 3.730s | 4385.849us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 8.770s | 2649.842us | 1 | 1 | 100.00 | |