Simulation Results: edn

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.27 %
  • code
  • 79.83 %
  • assert
  • 94.22 %
  • func
  • 75.76 %
  • line
  • 97.34 %
  • branch
  • 90.62 %
  • cond
  • 86.60 %
  • toggle
  • 76.90 %
  • FSM
  • 47.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.960s 17.190us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.210s 22.520us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 17.948us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.700s 58.494us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.940s 16.676us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.940s 17.123us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 17.948us 1 1 100.00
edn_csr_aliasing 0.940s 16.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.010s 42.519us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.010s 42.519us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.010s 42.519us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 27.467us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 36.983us 1 1 100.00
errs 1 1 100.00
edn_err 1.030s 53.628us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 26.984us 1 1 100.00
edn_disable_auto_req_mode 0.950s 18.983us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.120s 522.738us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.200s 44.374us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 18.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.380s 77.868us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.380s 77.868us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.210s 22.520us 1 1 100.00
edn_csr_rw 0.840s 17.948us 1 1 100.00
edn_csr_aliasing 0.940s 16.676us 1 1 100.00
edn_same_csr_outstanding 0.870s 73.620us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.210s 22.520us 1 1 100.00
edn_csr_rw 0.840s 17.948us 1 1 100.00
edn_csr_aliasing 0.940s 16.676us 1 1 100.00
edn_same_csr_outstanding 0.870s 73.620us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.810s 264.472us 1 1 100.00
edn_sec_cm 6.110s 742.876us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 24.968us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 36.983us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.110s 742.876us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.110s 742.876us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.110s 742.876us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.110s 742.876us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 36.983us 1 1 100.00
edn_sec_cm 6.110s 742.876us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 36.983us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.810s 264.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 59.180s 12076.105us 1 1 100.00