Simulation Results: flash_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.11 %
  • code
  • 94.43 %
  • assert
  • 88.97 %
  • func
  • 95.92 %
  • line
  • 95.98 %
  • branch
  • 97.10 %
  • cond
  • 93.75 %
  • toggle
  • 98.24 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
98.46%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 65.860s 117.307us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.230s 28.935us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 13.170s 99.665us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 45.130s 2276.636us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 21.880s 2381.220us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.330s 127.085us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
flash_ctrl_csr_aliasing 21.880s 2381.220us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.400s 83.221us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.550s 17.483us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.280s 192.059us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 14.850s 94.027us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1561.600s 426929.399us 1 1 100.00
flash_ctrl_hw_rma_reset 533.860s 150175.916us 1 1 100.00
flash_ctrl_lcmgr_intg 5.880s 54.412us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1262.580s 352828.240us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 93.430s 878.306us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.590s 21.640us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1555.560s 172322.699us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 44.180s 2404.625us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.940s 37.277us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.960s 29.689us 1 1 100.00
flash_ctrl_re_evict 15.550s 126.101us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 73.390s 112.909us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 73.390s 112.909us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 73.900s 17324.359us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.360s 427.097us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 376.270s 218.682us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 230.490s 1400.726us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 341.680s 399.831us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 762.730s 2743.485us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.140s 41.958us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 114.240s 1412.891us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.250s 24.753us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.960s 49.999us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 541.400s 2533.716us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 42.540s 22048.184us 1 1 100.00
flash_ctrl_otp_reset 45.300s 154.674us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1561.600s 426929.399us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 95.980s 6596.548us 1 1 100.00
flash_ctrl_intr_wr 49.610s 5759.645us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 85.840s 12414.107us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 359.600s 485226.357us 1 1 100.00
invalid_op 0 1 0.00
flash_ctrl_invalid_op 50.380s 3320.458us 0 1 0.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 32.890s 3424.035us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.710s 66.555us 1 1 100.00
flash_ctrl_ro_derr 92.250s 768.028us 1 1 100.00
flash_ctrl_rw_derr 137.840s 1659.423us 1 1 100.00
flash_ctrl_derr_detect 102.690s 830.892us 1 1 100.00
flash_ctrl_integrity 320.190s 6342.263us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.660s 233.034us 1 1 100.00
flash_ctrl_ro_serr 73.420s 1600.285us 1 1 100.00
flash_ctrl_rw_serr 122.330s 6681.133us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 35.390s 1301.250us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 47.190s 1950.357us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 131.700s 4962.851us 1 1 100.00
flash_ctrl_write_word_sweep 6.690s 42.194us 1 1 100.00
flash_ctrl_read_word_sweep 6.600s 46.681us 1 1 100.00
flash_ctrl_ro 60.460s 477.160us 1 1 100.00
flash_ctrl_rw 322.240s 15424.352us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.160s 906.103us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 618.690s 157529.102us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 33.430s 10082.388us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.960s 286.473us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.530s 114.789us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.190s 62.819us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.190s 62.819us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.170s 99.665us 1 1 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
flash_ctrl_csr_aliasing 21.880s 2381.220us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.910s 363.573us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 13.170s 99.665us 1 1 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
flash_ctrl_csr_aliasing 21.880s 2381.220us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.910s 363.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 31.690s 190.453us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 345.680s 698.495us 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 345.680s 698.495us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 345.680s 698.495us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.050s 115.270us 1 1 100.00
flash_ctrl_wr_intg 6.690s 61.281us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 65.860s 117.307us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 45.300s 154.674us 1 1 100.00
flash_ctrl_disable 10.250s 24.753us 1 1 100.00
flash_ctrl_sec_info_access 35.700s 911.652us 1 1 100.00
flash_ctrl_connect 8.960s 49.999us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.740s 24.667us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.400s 22.895us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 18.180s 22.875us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.250s 24.753us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.050s 115.270us 1 1 100.00
flash_ctrl_access_after_disable 5.590s 21.175us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 11.140s 27.957us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.250s 24.753us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.360s 427.097us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 322.240s 15424.352us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 122.330s 6681.133us 1 1 100.00
flash_ctrl_rw_derr 137.840s 1659.423us 1 1 100.00
flash_ctrl_integrity 320.190s 6342.263us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1561.600s 426929.399us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.180s 840.786us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.590s 91.737us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.340s 49.733us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1510.110s 4027.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.220s 303.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 10.570s 36.693us 1 1 100.00