Simulation Results: hmac

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.59 %
  • code
  • 97.95 %
  • assert
  • 96.42 %
  • func
  • 44.39 %
  • line
  • 99.74 %
  • branch
  • 99.50 %
  • cond
  • 96.40 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.920s 418.143us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.100s 197.052us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.870s 75.560us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.580s 309.896us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.620s 397.567us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.860s 40.895us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.870s 75.560us 1 1 100.00
hmac_csr_aliasing 2.620s 397.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 18.770s 1608.044us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 6.010s 141.991us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 198.410s 9087.134us 1 1 100.00
hmac_test_sha384_vectors 19.560s 240.224us 1 1 100.00
hmac_test_sha512_vectors 21.900s 398.305us 1 1 100.00
hmac_test_hmac256_vectors 9.330s 644.205us 1 1 100.00
hmac_test_hmac384_vectors 7.100s 334.438us 1 1 100.00
hmac_test_hmac512_vectors 8.870s 518.709us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 10.480s 755.145us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 63.290s 2833.254us 1 1 100.00
error 1 1 100.00
hmac_error 40.740s 978.895us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 50.260s 6113.836us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.920s 418.143us 1 1 100.00
hmac_long_msg 18.770s 1608.044us 1 1 100.00
hmac_back_pressure 6.010s 141.991us 1 1 100.00
hmac_datapath_stress 63.290s 2833.254us 1 1 100.00
hmac_burst_wr 10.480s 755.145us 1 1 100.00
hmac_stress_all 1919.430s 90228.514us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.920s 418.143us 1 1 100.00
hmac_long_msg 18.770s 1608.044us 1 1 100.00
hmac_back_pressure 6.010s 141.991us 1 1 100.00
hmac_datapath_stress 63.290s 2833.254us 1 1 100.00
hmac_wipe_secret 50.260s 6113.836us 1 1 100.00
hmac_test_sha256_vectors 198.410s 9087.134us 1 1 100.00
hmac_test_sha384_vectors 19.560s 240.224us 1 1 100.00
hmac_test_sha512_vectors 21.900s 398.305us 1 1 100.00
hmac_test_hmac256_vectors 9.330s 644.205us 1 1 100.00
hmac_test_hmac384_vectors 7.100s 334.438us 1 1 100.00
hmac_test_hmac512_vectors 8.870s 518.709us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.920s 418.143us 1 1 100.00
hmac_long_msg 18.770s 1608.044us 1 1 100.00
hmac_back_pressure 6.010s 141.991us 1 1 100.00
hmac_datapath_stress 63.290s 2833.254us 1 1 100.00
hmac_burst_wr 10.480s 755.145us 1 1 100.00
hmac_error 40.740s 978.895us 1 1 100.00
hmac_wipe_secret 50.260s 6113.836us 1 1 100.00
hmac_test_sha256_vectors 198.410s 9087.134us 1 1 100.00
hmac_test_sha384_vectors 19.560s 240.224us 1 1 100.00
hmac_test_sha512_vectors 21.900s 398.305us 1 1 100.00
hmac_test_hmac256_vectors 9.330s 644.205us 1 1 100.00
hmac_test_hmac384_vectors 7.100s 334.438us 1 1 100.00
hmac_test_hmac512_vectors 8.870s 518.709us 1 1 100.00
hmac_stress_all 1919.430s 90228.514us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1919.430s 90228.514us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.860s 11.880us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 12.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.490s 112.632us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.490s 112.632us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.100s 197.052us 1 1 100.00
hmac_csr_rw 0.870s 75.560us 1 1 100.00
hmac_csr_aliasing 2.620s 397.567us 1 1 100.00
hmac_same_csr_outstanding 2.140s 162.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.100s 197.052us 1 1 100.00
hmac_csr_rw 0.870s 75.560us 1 1 100.00
hmac_csr_aliasing 2.620s 397.567us 1 1 100.00
hmac_same_csr_outstanding 2.140s 162.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 3.260s 528.693us 1 1 100.00
hmac_sec_cm 1.310s 148.366us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.260s 528.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.920s 418.143us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.840s 332.749us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 198.070s 9321.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.040s 33.330us 1 1 100.00