Simulation Results: lc_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.02 %
  • code
  • 83.07 %
  • assert
  • 94.13 %
  • func
  • 89.86 %
  • line
  • 97.08 %
  • branch
  • 93.67 %
  • cond
  • 79.03 %
  • toggle
  • 74.27 %
  • FSM
  • 71.28 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.290s 375.586us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.080s 22.464us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 28.587us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.040s 70.610us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 53.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.530s 32.968us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 28.587us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 53.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.670s 122.713us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.390s 202.046us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 95.024us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.910s 84.873us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.070s 1968.964us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_prog_failure 1.910s 84.873us 1 1 100.00
lc_ctrl_errors 7.070s 1968.964us 1 1 100.00
lc_ctrl_security_escalation 5.210s 309.101us 1 1 100.00
lc_ctrl_jtag_state_failure 6.310s 5282.854us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.190s 309.710us 1 1 100.00
lc_ctrl_jtag_errors 23.820s 10009.013us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.560s 191.492us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.630s 44.002us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.690s 2982.080us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 12.050s 2196.526us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.210s 32.155us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.980s 198.833us 1 1 100.00
lc_ctrl_jtag_alert_test 0.990s 62.706us 1 1 100.00
lc_ctrl_jtag_smoke 12.090s 715.181us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.390s 3373.695us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.190s 309.710us 1 1 100.00
lc_ctrl_jtag_errors 23.820s 10009.013us 1 1 100.00
lc_ctrl_jtag_access 3.070s 104.727us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.510s 1309.418us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.870s 370.273us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.110s 53.027us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 1.490s 124.444us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.350s 144.028us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 140.508us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 140.508us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.080s 22.464us 1 1 100.00
lc_ctrl_csr_rw 0.730s 28.587us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 53.673us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.900s 15.608us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.080s 22.464us 1 1 100.00
lc_ctrl_csr_rw 0.730s 28.587us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 53.673us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.900s 15.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.510s 53.420us 1 1 100.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.510s 53.420us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.390s 202.046us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.290s 26.592us 0 1 0.00
lc_ctrl_sec_cm 7.380s 897.422us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.210s 309.101us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.670s 122.713us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.390s 3373.695us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.140s 332.714us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.140s 332.714us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.210s 700.531us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.210s 341.154us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.210s 341.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 84.720s 13361.949us 0 1 0.00