Simulation Results: lc_ctrl

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.94 %
  • code
  • 83.54 %
  • assert
  • 94.13 %
  • func
  • 89.15 %
  • line
  • 96.93 %
  • branch
  • 93.32 %
  • cond
  • 79.01 %
  • toggle
  • 76.87 %
  • FSM
  • 71.58 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.600s 93.040us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.360s 57.028us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 97.556us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.390s 52.323us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 14.592us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 82.645us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 97.556us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 14.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.770s 10.743us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 15.950s 743.074us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.020s 32.913us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.780s 66.004us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.550s 439.715us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_prog_failure 1.780s 66.004us 1 1 100.00
lc_ctrl_errors 6.550s 439.715us 1 1 100.00
lc_ctrl_security_escalation 6.780s 1255.486us 1 1 100.00
lc_ctrl_jtag_state_failure 4.040s 1022.161us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.630s 886.461us 1 1 100.00
lc_ctrl_jtag_errors 25.190s 2543.538us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 2.690s 295.489us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.610s 214.058us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.990s 346.841us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.070s 438.743us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.750s 22.132us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.680s 45.214us 1 1 100.00
lc_ctrl_jtag_alert_test 2.070s 263.477us 1 1 100.00
lc_ctrl_jtag_smoke 2.180s 1225.664us 1 1 100.00
lc_ctrl_jtag_state_post_trans 20.340s 807.204us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.630s 886.461us 1 1 100.00
lc_ctrl_jtag_errors 25.190s 2543.538us 1 1 100.00
lc_ctrl_jtag_access 2.170s 431.724us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.700s 2967.675us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.830s 516.962us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 74.988us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 5.670s 307.118us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.060s 41.107us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.760s 1815.273us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.760s 1815.273us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.360s 57.028us 1 1 100.00
lc_ctrl_csr_rw 0.920s 97.556us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 14.592us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.240s 29.891us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.360s 57.028us 1 1 100.00
lc_ctrl_csr_rw 0.920s 97.556us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 14.592us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.240s 29.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 2.320s 120.777us 1 1 100.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.320s 120.777us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 15.950s 743.074us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3.350s 32.113us 0 1 0.00
lc_ctrl_sec_cm 7.260s 256.911us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.780s 1255.486us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.770s 10.743us 0 1 0.00
lc_ctrl_jtag_state_post_trans 20.340s 807.204us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.570s 347.886us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.570s 347.886us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.770s 513.407us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.990s 416.801us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.990s 416.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 24.020s 6760.591us 0 1 0.00