Simulation Results: pattgen

 
02/12/2025 19:22:53 sha: 06584dc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 8.000s 76.338us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 99.154us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 139.760us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 103.193us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 22.319us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 24.144us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 139.760us 1 1 100.00
pattgen_csr_aliasing 2.000s 22.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 531.000s 23268.379us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 11.000s 3636.109us 1 1 100.00
error 1 1 100.00
pattgen_error 7.000s 87.115us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 6.000s 301.949us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 5.000s 11.486us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 17.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 6.000s 34.323us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 6.000s 34.323us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 99.154us 1 1 100.00
pattgen_csr_rw 2.000s 139.760us 1 1 100.00
pattgen_csr_aliasing 2.000s 22.319us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 17.169us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 99.154us 1 1 100.00
pattgen_csr_rw 2.000s 139.760us 1 1 100.00
pattgen_csr_aliasing 2.000s 22.319us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 17.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 7.000s 39.988us 1 1 100.00
pattgen_tl_intg_err 3.000s 251.664us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 3.000s 251.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 39.000s 4863.179us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 8.000s 73.709us 1 1 100.00